David Harris
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0a6622a6fb
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hptw: Merged RV32/64 FSMs
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2021-07-17 11:55:24 -04:00 |
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David Harris
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cf0975c937
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hptw: FSM simplification
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2021-07-17 11:41:43 -04:00 |
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David Harris
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4469b5a4b3
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hptw: default state should be unreachable
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2021-07-17 11:33:16 -04:00 |
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David Harris
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9cee6c2281
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hptw: factored Misaligned
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2021-07-17 11:31:16 -04:00 |
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David Harris
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fa12727bbb
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hptw: factored HPTWRead
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2021-07-17 11:25:59 -04:00 |
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David Harris
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708f8cc3a2
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hptw: factored HPTWRead
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2021-07-17 11:25:52 -04:00 |
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David Harris
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ef63e1ab52
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hptw: factored pregen
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2021-07-17 11:11:10 -04:00 |
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David Harris
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880aa1c03a
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HPTW: more cleanup
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2021-07-17 04:55:01 -04:00 |
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David Harris
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a0f6c9aec1
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HPTW: factored out DTLBWrite/ITLBWrite
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2021-07-17 04:44:23 -04:00 |
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David Harris
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08e494dd7d
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HPTW: factored out PageTableENtry
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2021-07-17 04:40:01 -04:00 |
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David Harris
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bd270acdb6
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more cleaning up FSM
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2021-07-17 04:35:51 -04:00 |
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David Harris
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6d8a6eeba0
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cleaning up FSM
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2021-07-17 04:26:41 -04:00 |
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David Harris
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330e500442
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Simplify FSM
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2021-07-17 04:12:31 -04:00 |
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David Harris
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03ef3f7f17
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Pulled TranslationPAdr mux out of HPTW FSM
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2021-07-17 04:06:26 -04:00 |
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David Harris
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5698433463
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Simplified bad PTE detection
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2021-07-17 03:30:17 -04:00 |
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David Harris
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ac67342dd4
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Pulled out shared PTEReg
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2021-07-17 03:21:09 -04:00 |
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David Harris
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86ca9abe42
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Flip-flop clean-up
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2021-07-17 03:15:47 -04:00 |
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David Harris
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9a15a2f7df
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Flip-flop clean-up
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2021-07-17 03:12:24 -04:00 |
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David Harris
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8241dd4599
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Flip-flop clean-up
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2021-07-17 03:10:17 -04:00 |
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David Harris
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a8a5fa4b3c
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Started pagetablewalker cleanup: combined state flops shared for both RV versions
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2021-07-17 02:53:52 -04:00 |
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David Harris
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b65788d165
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Replaced separate PageTypeF and PageTypeM with common PageType
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2021-07-17 02:31:23 -04:00 |
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Ross Thompson
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46bce70e42
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Fixed walker fault interaction with dcache.
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2021-07-16 12:22:13 -05:00 |
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Ross Thompson
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e0f719d513
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Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues.
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2021-07-16 11:12:57 -05:00 |
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Kip Macsai-Goren
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abd5b1c02d
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Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction.
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2021-07-15 18:30:29 -04:00 |
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Ross Thompson
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e5d624c1fa
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Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.
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2021-07-15 11:56:35 -05:00 |
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Ross Thompson
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fa26aec588
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Merge branch 'main' into dcache
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2021-07-15 11:55:20 -05:00 |
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Ross Thompson
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b9902b0560
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Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits.
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2021-07-15 11:00:42 -05:00 |
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Ross Thompson
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ba1e1ec231
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Finally have the ptw correctly walking through the dcache to update the itlb.
Still not working fully.
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2021-07-14 22:26:07 -05:00 |
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Ross Thompson
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3e57c899a2
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Partially working changes to support uncached memory access. Not sure what CommitedM is.
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2021-07-13 17:24:59 -05:00 |
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David Harris
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861ef5e1cb
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Replaced .or with or_rows structural code in MMU read circuitry for synthesis.
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2021-07-13 09:32:02 -04:00 |
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David Harris
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d3ab6b192a
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added missing tlbmixer.sv
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2021-07-09 19:18:23 -04:00 |
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David Harris
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5c2f774c35
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Simplified tlbmixer mux to and-or
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2021-07-08 23:34:24 -04:00 |
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David Harris
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74b6d13195
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Fixed missing stall in InstrRet counter
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2021-07-08 20:08:04 -04:00 |
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Ross Thompson
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94c3fde724
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Renamed signal in LSU toLSU and fromLSU to toDCache and fromDCache.
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2021-07-08 18:03:52 -05:00 |
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David Harris
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4f1a85ca7c
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Eliminate reserved bits from TLB RAM
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2021-07-08 17:35:00 -04:00 |
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David Harris
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38772de21f
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Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram
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2021-07-08 16:58:11 -04:00 |
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David Harris
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1190729896
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TLB cleanup to match diagrams
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2021-07-08 16:52:06 -04:00 |
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David Harris
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5d5274ec73
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-07 06:32:29 -04:00 |
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David Harris
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2bab3f769b
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Renamed tlb ReadLines to Matches
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2021-07-07 06:32:26 -04:00 |
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Abe
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b757c96b2d
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Changed SvMode to SVMode on line 76
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2021-07-06 23:28:58 -04:00 |
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David Harris
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af619dcd75
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Added ASID matching for CAM
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2021-07-06 18:56:25 -04:00 |
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Kip Macsai-Goren
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8350622f65
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-06 18:54:41 -04:00 |
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David Harris
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7d857cf4bd
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more TLB name touchups
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2021-07-06 18:39:30 -04:00 |
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Kip Macsai-Goren
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e08a578908
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fixed upper bits page fault signal
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2021-07-06 18:32:47 -04:00 |
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David Harris
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2e2aa2a972
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connected signals in tlb by name instead of .*
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2021-07-06 17:22:10 -04:00 |
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David Harris
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ee3a321002
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changed tlbphysicalpagemask to structural
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2021-07-06 17:16:58 -04:00 |
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David Harris
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f960561cbb
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changed tlbphysicalpagemask to structural
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2021-07-06 17:08:04 -04:00 |
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David Harris
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032c38b7e7
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MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB
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2021-07-06 15:29:42 -04:00 |
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Ross Thompson
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3345ed7ff4
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Merged several of the load/store/instruction access faults inside the mmu.
Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
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2021-07-06 13:43:53 -05:00 |
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David Harris
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30fdd7abc8
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Cleaned up tlb output muxing
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2021-07-06 10:44:05 -04:00 |
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