Katherine Parry
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9d281b2604
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fcvt.sv paramaterized
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2022-05-26 20:48:22 +00:00 |
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DTowersM
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7ffef6ccfa
|
fixed indent spacing (cosmetic change)
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2022-05-26 19:04:21 +00:00 |
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slmnemo
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d1421b88ad
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Added line to testbench to prevent annoying burst sizes
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2022-05-25 17:29:45 -07:00 |
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DTowersM
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de60b15cfe
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-26 00:12:46 +00:00 |
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slmnemo
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b5476204da
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see commit 9042cc3c
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2022-05-25 17:10:59 -07:00 |
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DTowersM
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a1cda79cd5
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Merge branch 'embench' into main
embench contained the working makefiles for embench and is being merged into main as it working and done
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2022-05-26 00:10:50 +00:00 |
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DTowersM
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3f7eddbc89
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working makefile for embench and removed testbench-f64
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2022-05-26 00:08:18 +00:00 |
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slmnemo
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4e5505f301
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added logic to prevent cache line length from exceeding the max size of a burst.
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2022-05-25 17:03:15 -07:00 |
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Katherine Parry
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f35450207f
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single and double conversions pass all tests
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2022-05-25 23:02:02 +00:00 |
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slmnemo
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e3a7e3e2f3
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changes suggested by ben, hopefully fixing buildroot (which is now not running)
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2022-05-20 18:42:38 -07:00 |
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Katherine Parry
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5d34db85b2
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Fixed unpacker bug LT EQ LE pass testfloat
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2022-05-20 17:19:50 +00:00 |
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slmnemo
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79c28d34dc
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-05-19 17:51:45 -07:00 |
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slmnemo
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8b27c1884e
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Fixed buildroot by adding a second .
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2022-05-19 17:49:32 -07:00 |
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slmnemo
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89c7438424
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parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do
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2022-05-19 16:21:38 -07:00 |
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Katherine Parry
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6f2d8c24ad
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Bug fixed in unpacker and sub/add/mul tests pass TestFloat
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2022-05-19 20:31:23 +00:00 |
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Katherine Parry
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738bbf6479
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Added fp tests - doesnpass yet
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2022-05-19 16:32:30 +00:00 |
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slmnemo
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e4f0f55530
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Updated testbench to initialize using force and releases storing zero in all memory locations in branch predictor. Fixed arch64i bug related to failing bge due to an incorrect signature.
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2022-05-17 01:04:13 +00:00 |
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slmnemo
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7656e3031c
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quit
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2022-05-17 01:03:09 +00:00 |
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David Harris
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14f9f41d2d
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Partitioned privileged pipeline registers into module
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2022-05-12 20:45:45 +00:00 |
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David Harris
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39ceb3a550
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Partitioned privilege mode fsm into new module
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2022-05-12 16:16:42 +00:00 |
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David Harris
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1aa3e65bae
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Removed more unused signals, simplified csri state
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2022-05-12 15:10:10 +00:00 |
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mmasserfrye
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6cba6a92ba
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filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv
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2022-05-12 07:22:06 +00:00 |
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David Harris
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8166fd772e
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Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt
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2022-05-11 15:08:33 +00:00 |
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David Harris
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137b411bea
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Removed M suffix from interrupts because they are generated asynchronously to pipeline
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2022-05-11 14:41:55 +00:00 |
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David Harris
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7f42ff06d2
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SFENCE.VMA should be illegal in user mode
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2022-05-05 15:15:02 +00:00 |
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David Harris
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9b7aab122e
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wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts
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2022-05-05 14:37:21 +00:00 |
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David Harris
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1a7599ce94
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Changed WFI to stall pipeline in memory stage
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2022-05-05 02:03:44 +00:00 |
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Kip Macsai-Goren
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895a4f4832
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updated makefrag and tests.vh to reflect removed tests, new names
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2022-05-04 21:20:25 +00:00 |
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Kip Macsai-Goren
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75e90f193e
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added missing SIE test
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2022-04-29 19:54:29 +00:00 |
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Kip Macsai-Goren
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c0b56bfd27
|
renamed PIE-stack tests to status-mie for clarity
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2022-04-29 18:30:39 +00:00 |
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Kip Macsai-Goren
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c47ec36bc7
|
removed old unused tests from wally arch tests
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2022-04-28 18:14:08 +00:00 |
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Kip Macsai-Goren
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aedf0341af
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added 32 bit versions of new tests. all but timeout wait pass regression
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2022-04-28 18:14:07 +00:00 |
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Skylar Litz
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64a537c59b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-27 10:50:19 -07:00 |
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Skylar Litz
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f2b6842edb
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fix AttemptedInstructionCount from ground zero
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2022-04-27 10:45:40 -07:00 |
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Kip Macsai-Goren
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74b103fae4
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added working tests to test list, updated regression for new configs
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2022-04-25 19:18:15 +00:00 |
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Kip Macsai-Goren
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01f8bdfafc
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added new tests to tests.vh, comented out until they pass regression
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2022-04-25 18:22:44 +00:00 |
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David Harris
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1a8369b02b
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Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields
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2022-04-25 14:49:00 +00:00 |
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Ross Thompson
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e56b9f18d5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-21 09:52:42 -05:00 |
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Kip Macsai-Goren
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25d0f6305a
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added new tests to tests.vh
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2022-04-20 17:34:40 +00:00 |
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Kip Macsai-Goren
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324d3fcea5
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added working general trap tests to regression
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2022-04-20 06:48:01 +00:00 |
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Ross Thompson
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b94927d8a6
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-19 14:09:50 -05:00 |
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Kip Macsai-Goren
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121cc627f6
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Added working trap test to regression, fixed hanfling of some interrupts
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2022-04-18 07:22:16 +00:00 |
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Ross Thompson
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61dbf13a69
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Fixed bug I introduced by csrc cleanup and changes to ILA.
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2022-04-17 21:45:46 -05:00 |
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Ross Thompson
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3add26be64
|
fixed no forcing bug in linux testbench.
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2022-04-17 17:49:51 -05:00 |
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David Harris
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5bb521635e
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Experiments with prefix comparator; minor fixes in WFI and testbench warnings
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2022-04-17 21:43:12 +00:00 |
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Kip Macsai-Goren
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331efcedc4
|
added new tests to makefrag and tests.vh
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2022-04-17 21:00:36 +00:00 |
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David Harris
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c3bca40e05
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Added WFI to the testbench instruction name decoder
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2022-04-14 17:12:11 +00:00 |
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bbracker
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0e183be3e5
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fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM
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2022-04-14 09:23:21 -07:00 |
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bbracker
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489ce4269a
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fix ReadDataM forcing
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2022-04-13 15:32:00 -07:00 |
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Ross Thompson
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65573f07b7
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-13 13:39:47 -05:00 |
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bbracker
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016e960401
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change interrupt spoofing to happen at negative clock edges
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2022-04-13 04:31:23 -07:00 |
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bbracker
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3465d8cd32
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improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS
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2022-04-13 03:37:53 -07:00 |
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bbracker
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67ef47b25b
|
whoops forgot to update AttemptedInstructionCount in interrupt spoofing
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2022-04-13 00:49:37 -07:00 |
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bbracker
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6c3d274970
|
change testbench-linux to by default use attempted instruction count for warning/error messages
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2022-04-12 21:22:08 -07:00 |
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Ross Thompson
|
adb4e30c45
|
Missed the force on uart for no tracking.
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2022-04-12 19:37:44 -05:00 |
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Ross Thompson
|
56bea58a3c
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-10 13:41:27 -05:00 |
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Ross Thompson
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fc5eac6820
|
Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing.
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2022-04-10 13:27:54 -05:00 |
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bbracker
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c0c5733a1d
|
upgrade testbench interrupt forcing such that first m_timer interrupt now successfully spoofs
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2022-04-08 13:45:27 -07:00 |
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bbracker
|
23406d0926
|
small signs of life on new interrupt spoofing
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2022-04-08 12:32:30 -07:00 |
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Ross Thompson
|
1614996941
|
Fixed typo in tests.vh
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2022-04-07 16:28:28 -05:00 |
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Kip Macsai-Goren
|
c3a6b88acc
|
updated test signature locations
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2022-04-06 07:28:38 +00:00 |
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Katherine Parry
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c3d07b2c46
|
generating all testfloat vectors
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2022-04-04 17:17:12 +00:00 |
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Ross Thompson
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51dfa16f59
|
Updated the fpga test bench.
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2022-04-01 17:14:47 -05:00 |
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bbracker
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69a0f6e00b
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big interrupts refactor
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2022-03-30 13:22:41 -07:00 |
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Ross Thompson
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e4f4e1bd43
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-30 11:09:44 -05:00 |
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Ross Thompson
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839bede656
|
Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.
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2022-03-30 11:04:15 -05:00 |
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Ross Thompson
|
997c1b87fe
|
rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.
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2022-03-29 23:48:19 -05:00 |
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Ross Thompson
|
66e9380cfb
|
Partial fix to allow byte write enables with fpga and still get a preload to work.
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2022-03-29 19:12:29 -05:00 |
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Kip Macsai-Goren
|
d031c003ba
|
fixed arch bge test signature output location after update
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2022-03-29 20:45:18 +00:00 |
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Kip Macsai-Goren
|
a6d90a25c2
|
fixed signature location of the new periph with no compressed instructions
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2022-03-29 02:15:17 +00:00 |
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Skylar Litz
|
f91fb7a388
|
add AtemptedInstructionCount signal
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2022-03-26 21:28:57 +00:00 |
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Kip Macsai-Goren
|
7ae1d14191
|
added basic trap tests that do not pass regression yet. updated signature adresses
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2022-03-25 22:57:41 +00:00 |
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bbracker
|
6f6663cd67
|
fix multiple-context PLIC checkpoint generation
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2022-03-25 01:02:22 +00:00 |
|
bbracker
|
d33de3ef6b
|
tabs vs spaces disagreement
|
2022-03-24 17:11:41 -07:00 |
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bbracker
|
4b376e2834
|
1st attempt at multiple channel PLIC
|
2022-03-24 17:08:10 -07:00 |
|
Ross Thompson
|
71aad2d213
|
Moved WriteDataM register into LSU.
|
2022-03-23 14:17:59 -05:00 |
|
Ross Thompson
|
aa60b57fb3
|
Cleanup in testbench-linux.sv.
|
2022-03-22 22:34:38 -05:00 |
|
Ross Thompson
|
b2487f4b72
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-22 21:28:50 -05:00 |
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Ross Thompson
|
4ca9458534
|
added SIP, SIE, and SSTATUS to checkpoints. Can't seem to get the linux testbench to force SIP.
|
2022-03-22 21:28:34 -05:00 |
|
Ross Thompson
|
e6b42cb10f
|
Added spoof of uart addresses +0x2 and +0x6.
|
2022-03-22 16:52:27 -05:00 |
|
Katherine Parry
|
e3d01c875b
|
FMA parameterized and FMA testbench reworked
|
2022-03-19 19:39:03 +00:00 |
|
Ross Thompson
|
7a25d577ba
|
Added new asserts to testbench.
|
2022-03-11 15:41:53 -06:00 |
|
bbracker
|
742e8d98cd
|
fix up PLIC and UART checkpointing
|
2022-03-07 23:48:47 -08:00 |
|
bbracker
|
92e1583db5
|
change testbench-linux.sv to use new shared location of disassembly files
|
2022-03-07 20:04:08 -08:00 |
|
David Harris
|
e4d18f1808
|
removed more old 64priv tests
|
2022-03-04 03:57:19 +00:00 |
|
bbracker
|
c3e59ae2df
|
comment out nonfunctioning CSR-PERMISSIONS-M test
|
2022-03-04 00:11:55 +00:00 |
|
bbracker
|
79ff8d3c80
|
remove imperas32p tests
|
2022-03-04 00:06:18 +00:00 |
|
bbracker
|
87aad1d953
|
fix peripheral test and add it to regression
|
2022-03-02 23:44:39 +00:00 |
|
bbracker
|
4fe35aadf2
|
add rv32a tests to regression
|
2022-03-02 17:54:55 +00:00 |
|
bbracker
|
b6031bb15f
|
fix buildroot checkpointing and add it back to regression
|
2022-03-02 16:00:19 +00:00 |
|
bbracker
|
29179c6787
|
add LRSC test and add wally64a to regression
|
2022-03-02 07:09:37 +00:00 |
|
bbracker
|
a8e8cfb838
|
switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv
|
2022-03-01 03:11:43 +00:00 |
|
bbracker
|
d8ddda760b
|
deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test
|
2022-03-01 00:37:46 +00:00 |
|
David Harris
|
329fea9329
|
Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath
|
2022-02-28 20:50:51 +00:00 |
|
bbracker
|
ac114e1c6d
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-02-22 04:27:50 +00:00 |
|
bbracker
|
202bd2f8f8
|
change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
|
2022-02-22 03:46:08 +00:00 |
|
Kip Macsai-Goren
|
04892c5d38
|
added scratch register tests for 64 and 32 bits
|
2022-02-21 07:03:12 +00:00 |
|
Kip Macsai-Goren
|
324efa7d42
|
added 32 bit pma tests to regression even though they've been working fo a while
|
2022-02-18 19:43:24 +00:00 |
|
Kip Macsai-Goren
|
dcb5d0f6a9
|
Added misa test for both 32 and 64 bits
|
2022-02-18 19:41:50 +00:00 |
|
Kip Macsai-Goren
|
e16581d73d
|
added CSR permission and minfor to 32 bit tests
|
2022-02-15 20:19:14 +00:00 |
|