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830 Commits 14 Branches 1 Tag 31 MiB
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Author SHA1 Message Date
Jarred Allen
041149eaf7 Minor fixes in regression 2021-05-09 13:57:09 -04:00
Jarred Allen
c7f400262c Fix bug in regression script 2021-05-06 12:56:57 -04:00
Domenico Ottolia
e3624ab2e6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-04 20:22:31 -04:00
Domenico Ottolia
88ab07d456 Forgot to add csr permission tests to testbench 2021-05-04 20:20:22 -04:00
Jarred Allen
be029ba02c Clean up regression script and document it 2021-05-04 18:58:59 -04:00
ushakya22
682bc7b58e Added mip tests to testbench 2021-05-04 15:36:06 -04:00
Thomas Fleming
1ec6ad14f6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-04 15:22:21 -04:00
bbracker
8a7fc959eb small synthesis fixes 2021-05-04 15:21:01 -04:00
Thomas Fleming
19ac77d3fa Fix compiler warning in PMP checker 2021-05-04 15:18:08 -04:00
Domenico Ottolia
8398e653dd Re-add medeleg tests to testbench 2021-05-04 14:42:20 -04:00
Ross Thompson
a03a63a5c7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-04 13:04:20 -05:00
Ross Thompson
21acc45121 Fixed synthesis bug with icache valid bit. 2021-05-04 13:03:08 -05:00
ushakya22
2e225bd756 Updated CSR tests 2021-05-04 13:48:47 -04:00
Ross Thompson
52e4c49bbb Fixed icache pcmux control for handling miss spill miss. 2021-05-04 11:05:01 -05:00
Thomas Fleming
44ea58b771 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-04 03:14:38 -04:00
Thomas Fleming
3a3c88f5b1 Fix bug in PMP checker 
Now we only enforce PMP regions if at least one is non-null
 2021-05-04 03:14:07 -04:00
ushakya22
46f20745d7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-04 02:22:17 -04:00
ushakya22
b805b98a8c Added MIE tests to testbench 2021-05-04 02:22:01 -04:00
Thomas Fleming
c9e5af30fa Disable PMP checker to fix test loops 
There is a bug in the PMP checker where S or U mode attempts to make a
memory access while no PMP registers are set. We currently treat this as
a failure, when this should instead be allowed.
 2021-05-04 01:56:05 -04:00
Domenico Ottolia
1673ad6e27 Minor tweaks to mcause & scause tests 2021-05-04 01:33:49 -04:00
David Harris
45b0af497c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-04 01:19:57 -04:00
David Harris
d68fe44446 Fixed testbench to produce error when signature.output doesn't exist 2021-05-04 01:19:44 -04:00
Thomas Fleming
41a19153cc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-04 01:14:13 -04:00
Domenico Ottolia
67c7bfe34d Use correct begin_signature for rv64p/MCAUSE and rv64p/SCAUSE 2021-05-04 01:04:12 -04:00
David Harris
09836bae64 Removed WALLY-ADD and WALLY-SUB from rv6rp Makefrag that was causing make to break 2021-05-04 00:40:15 -04:00
Domenico Ottolia
973f32da47 Fix 32 bit privileged tests!!! 2021-05-04 00:16:19 -04:00
Thomas Fleming
a3b5ae9742 Restore original order of tests 2021-05-03 23:50:21 -04:00
Thomas Fleming
ad40464557 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-03 23:15:39 -04:00
Thomas Fleming
803a69efe6 Enable mmu tests in testbench 2021-05-03 23:15:23 -04:00
Domenico Ottolia
c0f054556c Fix bug with IllegalInstrFaultM not getting correct value 2021-05-03 22:48:03 -04:00
Domenico Ottolia
2669a6a0db Run all tests 2021-05-03 22:38:59 -04:00
Domenico Ottolia
4d70e22a6a Update cause tests to be longer 2021-05-03 22:38:26 -04:00
Domenico Ottolia
997c9ad5c0 Add mtvec and stvec tests to testbench 2021-05-03 22:19:50 -04:00
Shriya Nadgauda
780ad3eaf4 working testbench-imperas 2021-05-03 22:16:58 -04:00
Shriya Nadgauda
c5a306426a finishing merge conflict changes 2021-05-03 22:15:05 -04:00
Shriya Nadgauda
b7159652f6 merge conflict fixes 2021-05-03 22:12:30 -04:00
Shriya Nadgauda
968994c04a updated pipeline tests 2021-05-03 22:07:36 -04:00
Thomas Fleming
0254ca7bf6 Adjust attributes in PMA checker 2021-05-03 21:58:32 -04:00
Thomas Fleming
b7056c85bd Get MMU tests working in OVPsim 2021-05-03 21:58:05 -04:00
David Harris
afd6153044 Rolled back fflush on uart. Use -syncio in Modelsim command line instead. 2021-05-03 20:04:44 -04:00
David Harris
603c7712a9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 19:51:54 -04:00
David Harris
d07a7fd0f8 Flush uart print statements on \n 2021-05-03 19:51:51 -04:00
Elizabeth Hedenberg
a654b8a3d3 coremark update 2021-05-03 19:42:00 -04:00
David Harris
93466a0b2a Flush uart print statements on \n 2021-05-03 19:41:37 -04:00
David Harris
e265aa4d41 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 19:37:56 -04:00
David Harris
58ce0fbbcc Flush uart print statements on \n 2021-05-03 19:37:45 -04:00
Elizabeth Hedenberg
2d1d929485 coremark print statment 2021-05-03 19:35:08 -04:00
Elizabeth Hedenberg
2a33673e3c coremark updates 2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg
b99fbc73f1 coremark update 2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg
7f5b8e63ed Coremark objump push 2021-05-03 19:35:07 -04:00