Ross Thompson
002c32d2ad
The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay.
2021-06-30 17:02:36 -05:00
Ross Thompson
9ec624702d
Major rewrite of ptw to remove combo loop.
2021-06-30 16:25:03 -05:00
Ross Thompson
b2d8ba6742
The icache now correctly interlocks with the PTW on TLB miss.
2021-06-30 11:24:26 -05:00
Ross Thompson
dd84f2958e
Page table walker now walks the table.
...
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
2021-06-29 22:33:57 -05:00
Ross Thompson
bc9c944ba0
Don't use this branch walker still broken.
2021-06-28 17:26:11 -05:00
Ross Thompson
d80ebab941
AMO and LR/SC instructions now working correctly.
...
Page table walking is not working.
2021-06-25 15:42:07 -05:00
Ross Thompson
57a7074800
Some progress. Had to change how the page table walker got it's ready.
2021-06-25 15:07:41 -05:00
Ross Thompson
b4a788c341
Working through a combo loop.
2021-06-25 14:49:27 -05:00
Ross Thompson
d6c19e73f4
Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults.
2021-06-25 11:05:17 -05:00
Kip Macsai-Goren
d7e518991e
Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.
2021-06-24 20:01:11 -04:00
Kip Macsai-Goren
ac597d78c8
Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations.
2021-06-24 19:59:29 -04:00
Ross Thompson
6bab454b17
Works until pma checker breaks the simulation by reading HADDR rather than data physical address.
2021-06-24 14:42:59 -05:00
Ross Thompson
c02141697d
Fixed combo loop in between the page table walker and i/dtlb.
2021-06-24 13:47:10 -05:00
Ross Thompson
aeeaf6d919
Progress.
2021-06-24 13:05:22 -05:00
Kip Macsai-Goren
c8f80967a6
added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day.
2021-06-23 19:59:06 -04:00
Ross Thompson
286b4b5b26
Partial addition of page table walker arbiter.
2021-06-23 17:03:54 -05:00
Ross Thompson
9b8bcb8e57
Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two.
...
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
2021-06-23 16:43:22 -05:00
Ross Thompson
f74ecbb81e
Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.
2021-06-23 15:13:56 -05:00
Ross Thompson
349f6a9471
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-23 09:34:42 -05:00
David Harris
a514554eeb
Reduced complexity of pmpadrdec
2021-06-23 03:03:52 -04:00
David Harris
2060a5c2f8
Reduced complexity of pmpadrdec
2021-06-23 02:31:50 -04:00
David Harris
fa51ab9f68
Refactored pmachecker to have adrdecs used in uncore
2021-06-23 01:41:00 -04:00
David Harris
6be0a3b8df
renamed dmem to lsu and removed adrdec module from pmpadrdec
2021-06-22 23:03:43 -04:00
bbracker
fc851ca795
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-22 18:28:30 -04:00
bbracker
303f8e2a7f
give EBU a dedicated PMA unit as just an address decoder
2021-06-22 18:28:08 -04:00
Ross Thompson
67cf2e1c90
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-22 15:47:16 -05:00
Katherine Parry
353a27f12f
rv64f FLW passes imperas tests
2021-06-22 16:36:16 -04:00
Kip Macsai-Goren
7e06a3c04d
Fixed mask assignment error, made usage, variables more clear
2021-06-22 13:31:06 -04:00
Kip Macsai-Goren
2c41da0275
Continued fixing fsm to work right with svmode
2021-06-22 13:29:49 -04:00
Kip Macsai-Goren
3e19eba20d
updated so svmode actually causes the right state tranitions. fsm now stuck in idle loop
2021-06-22 11:21:11 -04:00
bbracker
9b27cd6fb7
added slack notifier for long sims
2021-06-22 08:31:41 -04:00
Ross Thompson
f79e5eaa47
Icache now uses physical lenght bits rather than XLEN.
2021-06-21 16:41:09 -05:00
Ross Thompson
3cbe4c9bc2
Improved some names in icache.
2021-06-21 16:40:37 -05:00
David Harris
7930c2ebb4
Commented out 100k tests to improve speed
2021-06-21 01:43:18 -04:00
David Harris
5d6dc82db2
Added Physical Address and Size to PMA Checker/MMU
2021-06-21 01:27:02 -04:00
David Harris
1ec90a5e1f
Reversed [0:...] with [...:0] in bus widths across the project
2021-06-21 01:17:08 -04:00
David Harris
d2ec04564b
Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals
2021-06-20 22:59:04 -04:00
bbracker
23f479d225
remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
2021-06-20 22:38:25 -04:00
bbracker
bf3c2dc089
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-20 22:29:40 -04:00
bbracker
3000c27acd
linux actually uses FPU now!
2021-06-20 22:29:21 -04:00
Katherine Parry
2b67f25683
all rv64f instructions except convert, divide, square root, and FLD pass
2021-06-20 20:24:09 -04:00
bbracker
2643130c41
read from MSTATUS workaround because QEMU has incorrect MSTATUS
2021-06-20 10:11:39 -04:00
bbracker
14ae87ff0a
testbench update b/c QEMU extends 32b CSRs to 64b
2021-06-20 09:24:19 -04:00
bbracker
83a0a37f8e
make xCOUNTEREN what buildroot expects it to be
2021-06-20 09:22:31 -04:00
bbracker
dc26f2a6d0
whoops wavedo typo
2021-06-20 05:36:54 -04:00
bbracker
c77aabdc6f
make buildroot ignore SSTATUS because QEMU did not originally log it
2021-06-20 05:31:24 -04:00
bbracker
918ff5093a
MSTATUS workaround
2021-06-20 04:48:09 -04:00
bbracker
069a79fafd
workaround for ignoring MTIME
2021-06-20 02:26:39 -04:00
bbracker
086f031b84
remove lingering busybear stuff from buildroot do files
2021-06-20 00:50:53 -04:00
bbracker
8462f248aa
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-20 00:40:44 -04:00
