cvw/wally-pipelined/src/wally/wallypipelinedhart.sv

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///////////////////////////////////////////
// wallypipelinedhart.sv
//
// Written: David_Harris@hmc.edu 9 January 2021
// Modified:
//
// Purpose: Pipelined RISC-V Processor
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-config.vh"
/* verilator lint_on UNUSED */
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module wallypipelinedhart (
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input logic clk, reset,
// Privileged
input logic TimerIntM, ExtIntM, SwIntM,
input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT,
// Bus Interface
input logic [`AHBW-1:0] HRDATA,
input logic HREADY, HRESP,
output logic HCLK, HRESETn,
output logic [31:0] HADDR,
output logic [`AHBW-1:0] HWDATA,
output logic HWRITE,
output logic [2:0] HSIZE,
output logic [2:0] HBURST,
output logic [3:0] HPROT,
output logic [1:0] HTRANS,
output logic HMASTLOCK,
// Delayed signals for subword write
output logic [2:0] HADDRD,
output logic [3:0] HSIZED,
output logic HWRITED
);
// logic [1:0] ForwardAE, ForwardBE;
logic StallF, StallD, StallE, StallM, StallW;
logic FlushF, FlushD, FlushE, FlushM, FlushW;
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logic RetM, TrapM;
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// new signals that must connect through DP
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logic MulDivE, W64E;
logic CSRReadM, CSRWriteM, PrivilegedM;
logic [1:0] AtomicE;
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logic [1:0] AtomicM;
logic [`XLEN-1:0] SrcAE, SrcBE;
logic [`XLEN-1:0] SrcAM;
logic [2:0] Funct3E;
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// logic [31:0] InstrF;
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logic [31:0] InstrD, InstrM;
logic [`XLEN-1:0] PCF, PCE, PCM, PCLinkE;
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logic [`XLEN-1:0] PCTargetE;
logic [`XLEN-1:0] CSRReadValW, MulDivResultW;
logic [`XLEN-1:0] PrivilegedNextPCM;
logic [1:0] MemRWM;
logic InstrValidM;
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logic InstrMisalignedFaultM;
logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
logic ITLBInstrPageFaultF, DTLBLoadPageFaultM, DTLBStorePageFaultM;
logic WalkerInstrPageFaultF, WalkerLoadPageFaultM, WalkerStorePageFaultM;
logic LoadMisalignedFaultM, LoadAccessFaultM;
logic StoreMisalignedFaultM, StoreAccessFaultM;
logic [`XLEN-1:0] InstrMisalignedAdrM;
logic InvalidateICacheM, FlushDCacheM;
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logic PCSrcE;
logic CSRWritePendingDEM;
logic DivBusyE;
logic LoadStallD, StoreStallD, MulDivStallD, CSRRdStallD;
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logic SquashSCW;
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// floating point unit signals
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logic [2:0] FRM_REGW;
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logic [4:0] RdM, RdW;
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logic FStallD;
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logic FWriteIntE, FWriteIntM, FWriteIntW;
logic [`XLEN-1:0] FWriteDataE;
logic [`XLEN-1:0] FIntResM;
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logic FDivBusyE;
logic IllegalFPUInstrD, IllegalFPUInstrE;
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logic FRegWriteM;
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logic FPUStallD;
logic [4:0] SetFflagsM;
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// memory management unit signals
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logic ITLBWriteF;
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logic ITLBFlushF, DTLBFlushM;
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logic ITLBMissF;
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logic [`XLEN-1:0] SATP_REGW;
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logic STATUS_MXR, STATUS_SUM, STATUS_MPRV;
logic [1:0] STATUS_MPP;
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logic [1:0] PrivilegeModeW;
logic [`XLEN-1:0] PTE;
logic [1:0] PageType;
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// PMA checker signals
var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0];
var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0];
// IMem stalls
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logic ICacheStallF;
logic LSUStall;
// cpu lsu interface
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logic [2:0] Funct3M;
logic [`XLEN-1:0] MemAdrM, MemAdrE, WriteDataM;
logic [`XLEN-1:0] ReadDataM;
logic [`XLEN-1:0] ReadDataW;
logic CommittedM;
// AHB ifu interface
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logic [`PA_BITS-1:0] InstrPAdrF;
logic [`XLEN-1:0] InstrRData;
logic InstrReadF;
logic InstrAckF;
// AHB LSU interface
logic [`PA_BITS-1:0] DCtoAHBPAdrM;
logic DCtoAHBReadM;
logic DCtoAHBWriteM;
logic DCfromAHBAck;
logic [`XLEN-1:0] DCfromAHBReadData;
logic [`XLEN-1:0] DCtoAHBWriteData;
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logic BPPredWrongE;
logic BPPredDirWrongM;
logic BTBPredPCWrongM;
logic RASPredPCWrongM;
logic BPPredClassNonCFIWrongM;
logic [4:0] InstrClassM;
logic InstrAccessFaultF;
logic [2:0] DCtoAHBSizeM;
logic ExceptionM;
logic PendingInterruptM;
logic DCacheMiss;
logic DCacheAccess;
logic BreakpointFaultM, EcallFaultM;
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ifu ifu(
.clk, .reset,
.StallF, .StallD, .StallE, .StallM, .StallW,
.FlushF, .FlushD, .FlushE, .FlushM, .FlushW,
.InstrInF(InstrRData), .InstrAckF, .PCF, .InstrPAdrF, .InstrReadF, .ICacheStallF,
.PCLinkE, .PCSrcE, .PCTargetE, .PCE,
.BPPredWrongE,
.RetM, .TrapM,
.PrivilegedNextPCM, .InvalidateICacheM,
.InstrD, .InstrM,
.PCM, .InstrClassM,
.BPPredDirWrongM,.BTBPredPCWrongM,.RASPredPCWrongM, .BPPredClassNonCFIWrongM,
.IllegalBaseInstrFaultD, .ITLBInstrPageFaultF, .IllegalIEUInstrFaultD,
.InstrMisalignedFaultM, .InstrMisalignedAdrM,
.PrivilegeModeW, .PTE, .PageType, .SATP_REGW,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
.ITLBWriteF, .ITLBFlushF,
.WalkerInstrPageFaultF,
.ITLBMissF,
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
.InstrAccessFaultF
); // instruction fetch unit: PC, branch prediction, instruction cache
ieu ieu(.*); // integer execution unit: integer register file, datapath and controller
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lsu lsu(.clk(clk),
.reset(reset),
.StallM(StallM),
.FlushM(FlushM),
.StallW(StallW),
.FlushW(FlushW),
// CPU interface
.MemRWM(MemRWM),
.Funct3M(Funct3M),
.Funct7M(InstrM[31:25]),
.AtomicM(AtomicM),
.ExceptionM(ExceptionM),
.PendingInterruptM(PendingInterruptM),
.CommittedM(CommittedM),
.DCacheMiss,
.DCacheAccess,
.SquashSCW(SquashSCW),
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//.DataMisalignedM(DataMisalignedM),
.MemAdrE(MemAdrE),
.MemAdrM(MemAdrM),
.WriteDataM(WriteDataM),
.ReadDataM(ReadDataM),
.FlushDCacheM,
// connected to ahb (all stay the same)
.DCtoAHBPAdrM(DCtoAHBPAdrM),
.DCtoAHBReadM(DCtoAHBReadM),
.DCtoAHBWriteM(DCtoAHBWriteM),
.DCfromAHBAck(DCfromAHBAck),
.DCfromAHBReadData(DCfromAHBReadData),
.DCtoAHBWriteData(DCtoAHBWriteData),
.DCtoAHBSizeM(DCtoAHBSizeM),
// connect to csr or privilege and stay the same.
.PrivilegeModeW(PrivilegeModeW), // connects to csr
.PMPCFG_ARRAY_REGW(PMPCFG_ARRAY_REGW), // connects to csr
.PMPADDR_ARRAY_REGW(PMPADDR_ARRAY_REGW), // connects to csr
// hptw keep i/o
.SATP_REGW(SATP_REGW), // from csr
.STATUS_MXR(STATUS_MXR), // from csr
.STATUS_SUM(STATUS_SUM), // from csr
.STATUS_MPRV(STATUS_MPRV), // from csr
.STATUS_MPP(STATUS_MPP), // from csr
.DTLBFlushM(DTLBFlushM), // connects to privilege
.DTLBLoadPageFaultM(DTLBLoadPageFaultM), // connects to privilege
.DTLBStorePageFaultM(DTLBStorePageFaultM), // connects to privilege
.LoadMisalignedFaultM(LoadMisalignedFaultM), // connects to privilege
.LoadAccessFaultM(LoadAccessFaultM), // connects to privilege
.StoreMisalignedFaultM(StoreMisalignedFaultM), // connects to privilege
.StoreAccessFaultM(StoreAccessFaultM), // connects to privilege
.PCF(PCF),
.ITLBMissF(ITLBMissF),
.PTE(PTE),
.PageType,
.ITLBWriteF(ITLBWriteF),
.WalkerInstrPageFaultF(WalkerInstrPageFaultF),
.WalkerLoadPageFaultM(WalkerLoadPageFaultM),
.WalkerStorePageFaultM(WalkerStorePageFaultM),
.LSUStall(LSUStall)); // change to LSUStall
ahblite ebu(// IFU connections
.InstrPAdrF(InstrPAdrF),
.InstrReadF(InstrReadF),
.InstrRData(InstrRData),
.InstrAckF(InstrAckF),
// LSU connections
.DCtoAHBPAdrM(DCtoAHBPAdrM), // rename to DCtoAHBPAdrM
.DCtoAHBReadM(DCtoAHBReadM), // rename to DCtoAHBReadM
.DCtoAHBWriteM(DCtoAHBWriteM), // rename to DCtoAHBWriteM
.DCtoAHBWriteData(DCtoAHBWriteData),
.DCfromAHBReadData(DCfromAHBReadData),
.DCfromAHBAck(DCfromAHBAck),
// remove these
.MemSizeM(DCtoAHBSizeM[1:0]), // *** depends on XLEN should be removed
.UnsignedLoadM(1'b0),
.AtomicMaskedM(2'b00),
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.*);
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muldiv mdu(.*); // multiply and divide unit
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hazard hzu(.*); // global stall and flush control
// Priveleged block operates in M and W stages, handling CSRs and exceptions
privileged priv(.*);
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fpu fpu(.*); // floating point unit
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endmodule