Huda-10xe
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c1eab9e778
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Updates to WallyTracer
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2024-12-05 06:55:23 -08:00 |
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Huda-10xe
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617434ac32
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Changes to Tracer for VM covergae
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2024-12-05 00:04:58 -08:00 |
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Rose Thompson
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3c848cd16c
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Fixed bug in the wally tracer to support hptw pte accesses.
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2024-12-03 09:56:03 -06:00 |
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Huda-10xe
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54e09df77c
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Removing debug signals
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2024-12-03 04:10:22 -08:00 |
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Huda-10xe
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ffdaca2760
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Removing debug signals
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2024-12-03 04:09:11 -08:00 |
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Huda-10xe
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4591d625d5
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Added another signal for VM Coverage
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2024-12-03 03:56:30 -08:00 |
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David Harris
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ec3143f014
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Updated warning in ramxdetector
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2024-11-29 12:03:14 -08:00 |
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David Harris
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155d1d511b
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Fixed funct7 code for sinval.vma (issue #1154)
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2024-11-29 11:39:24 -08:00 |
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David Harris
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05189d102a
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Modifying tracer toward being able to run non-gc configurations in lockstep
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2024-11-26 22:09:11 -08:00 |
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David Harris
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028ffe9f4a
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Removing obsolete ***
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2024-11-20 07:23:51 -08:00 |
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Rose Thompson
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fcf4ca1417
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Disabled tracer print.
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2024-11-15 08:32:43 -06:00 |
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Rose Thompson
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3596be433c
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Fixed the tracer so that traps don't clear the instruction or PC bits.
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2024-11-15 08:31:19 -06:00 |
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David Harris
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c02a649c3b
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Fixed warnings related to tracer variables
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2024-11-15 05:33:16 -08:00 |
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Jordan Carlin
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9d2a5c6e03
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Fix wallyTracer bug
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2024-11-14 15:31:10 -08:00 |
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Jordan Carlin
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51d7eea98a
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Merge branch 'main' of https://github.com/openhwgroup/cvw into rvvi32
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2024-11-14 15:04:11 -08:00 |
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Jordan Carlin
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61c5d035e9
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Add mseccfg shell to wallyTracer and reformat CSRs
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2024-11-14 15:03:13 -08:00 |
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Rose Thompson
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5e4f4c2072
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Simple change to ensure Trapped instructions are included with rvvi as
valid instructions. Required for functional coverage.
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2024-11-14 16:14:02 -06:00 |
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Jordan Carlin
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14e9a39523
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pmps working for RVVI in RV32
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2024-11-13 22:12:11 -08:00 |
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Jordan Carlin
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d666a0dd7b
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Update formatting in an attempt to understand what's happening in this file
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2024-11-13 18:26:53 -08:00 |
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Jordan Carlin
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017b3e9872
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Fix 32 bit CSRs in wallyTracer
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2024-11-13 17:01:01 -08:00 |
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Rose Thompson
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77d47e531f
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Merge branch 'main' into lrufixes
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2024-11-13 10:34:21 -06:00 |
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Rose Thompson
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2fe73f8174
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Replaced double | and & with single. We were having issues with these verilator giving a warning about the parameter widths not matching. However the warning is not occuring anymore.
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2024-11-13 00:02:51 -06:00 |
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Rose Thompson
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8993432928
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Resolved issue with questa not liking the TEST +arg as a generate.
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2024-11-12 23:57:30 -06:00 |
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Rose Thompson
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ef7072b7c2
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Merge branch 'main' into lrufixes
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2024-11-12 17:57:28 -06:00 |
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Rose Thompson
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8659d6efdb
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Resolved all CacheSim.py vs Wally mismaches.
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2024-11-12 17:24:06 -06:00 |
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Rose Thompson
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57fbd35484
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Fixed lint errors in loggers.sv with Kaitlin.
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2024-11-12 15:03:30 -06:00 |
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Rose Thompson
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b7b7c79726
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CBO.FLUSH was not clearing the valid bit if the cacheline was clean.
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2024-11-12 14:16:55 -06:00 |
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Rose Thompson
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5cc1fd4a85
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Getting closer. Oly the wally64priv tests mismatch between the cachesim and wally.
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2024-11-12 12:08:14 -06:00 |
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Rose Thompson
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8a4868ac57
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Resolved a bug in the cache but there are still mismatches with the cache simulator.
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2024-11-12 11:35:29 -06:00 |
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Rose Thompson
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0cf7b2e45a
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Progress on fixing the cache simulator to support cbo instructions.
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2024-11-11 16:37:17 -06:00 |
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Rose Thompson
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8fb1673ab3
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Updated email address authorship for my files.
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2024-10-15 10:27:53 -05:00 |
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Huda-10xe
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b77df83b59
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Adding DUT signals to the tracer for VM Coverage
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2024-10-07 03:52:36 -07:00 |
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Huda-10xe
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24f97fa696
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Adding DUT signals to the tracer for VM Coverage
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2024-10-07 03:49:43 -07:00 |
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Huda-10xe
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0817c69152
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Adding priv coverage to ISACOV
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2024-10-07 03:44:35 -07:00 |
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Rose Thompson
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1345a0f315
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2024-09-24 10:13:50 -05:00 |
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David Harris
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6157023d16
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2024-08-29 15:07:18 -07:00 |
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David Harris
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0e9e7d0a49
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Fixed wallyTracer floating-point register FLEN
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2024-08-29 11:11:19 -07:00 |
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Rose Thompson
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6ad2c2e7a6
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Merge pull request #935 from davidharrishmc/dev
Added lockstep support for RV32. Not all wally privileged tests pass…
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2024-08-29 10:45:17 -07:00 |
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David Harris
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26f3c2a607
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Added lockstep support for RV32. Not all wally privileged tests pass yet
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2024-08-29 10:44:37 -07:00 |
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Rose Thompson
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113d71f1a0
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More name updates.
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2024-08-21 10:51:24 -07:00 |
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Rose Thompson
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f603d21826
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Updated my name in multiple locations.
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2024-08-21 10:50:39 -07:00 |
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David Harris
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010038ec32
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Depricate conditional generation based on A_SUPPORTED, which is now computed from ZALRSC_SUPPORTED and ZAAMO_SUPPORTED
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2024-08-08 05:27:35 -07:00 |
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David Harris
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fa98ae8c30
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Depricate conditional generation based on A_SUPPORTED, which is now computed from ZALRSC_SUPPORTED and ZAAMO_SUPPORTED
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2024-08-08 05:27:35 -07:00 |
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Rose Thompson
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7164841f83
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Added padding into the hw rvvi format.
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2024-08-06 18:34:46 -05:00 |
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Rose Thompson
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ce61429bdf
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Fixed the reset bug in wallyTracer.
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2024-07-24 13:32:46 -05:00 |
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Rose Thompson
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5a6e32576d
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Fixed the reset bug in wallyTracer.
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2024-07-24 13:32:46 -05:00 |
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Rose Thompson
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d0a5b278b7
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Factored out the rvvi testbench code into rvvitbwrapper.
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2024-07-24 13:10:57 -05:00 |
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Rose Thompson
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13db14db6b
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Factored out the rvvi testbench code into rvvitbwrapper.
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2024-07-24 13:10:57 -05:00 |
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David Harris
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f30cc46ec5
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Disable misaligned accesses in imperas configuration and check misaligned support requires D$
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2024-07-21 08:26:07 -07:00 |
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David Harris
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f5f8a6c50c
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Disable misaligned accesses in imperas configuration and check misaligned support requires D$
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2024-07-21 08:26:07 -07:00 |
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