1641 Commits

Author	SHA1	Message	Date
Rose Thompson	d31622fa21	Merge pull request #1103 from JacobPease/main ... Made minor changes to the controller to clean up the logic. Still need to simplify the first always block.	2024-12-03 17:03:43 -06:00
David Harris	155d1d511b	Fixed funct7 code for sinval.vma (issue #1154)	2024-11-29 11:39:24 -08:00
David Harris	58bfc27c63	Fixed decoder for illegal 0b1e0c33 issue #1152	2024-11-29 11:20:12 -08:00
David Harris	cf47dd7e6b	Fixed bmu shift decode logic: bad funct7 for variable shifts, commented better, removed unnecessary guard	2024-11-29 05:58:14 -08:00
David Harris	722dc9bfda	Throw illegal instruction for RV64 W-type shifts with amounts > 31	2024-11-28 16:34:43 -08:00
David Harris	3f6611dd3a	Fixed fmv.d.x / fmv.x.d only on RV64	2024-11-28 14:47:58 -08:00
David Harris	f1072e46e1	fcvt to/fron long only allowed in RV64	2024-11-28 14:40:09 -08:00
David Harris	9116ffa45d	Fixed Issue #1147 that w-type shifts do not throw illegal instruction trap in RV32GC	2024-11-28 13:36:31 -08:00
David Harris	37c6879805	Fixed decoder bug that doesn't throw illegal instruction exception for RV32 immediate shifts by more than 31	2024-11-27 15:12:11 -08:00
Rose Thompson	2f04e5e597	Merge branch 'main' of github.com:rosethompson/cvw	2024-11-25 15:53:27 -06:00
Rose Thompson	7358c1fe67	Fixed sublte bug in the spi_fifo which allows for spurious write to fifo. Fixed fpga zsbl so that is uses read fifo interrupt pending (IP) rather than transmit fifo IP. Resolves issue with stalled load reading the wrong fifo status.	2024-11-25 15:50:29 -06:00
David Harris	ce7b036b78	Merge pull request #1109 from jordancarlin/lint ... More lint cleanup: remove unused params	2024-11-16 16:34:15 -08:00
Jacob Pease	2dcfe10013	Merged changes and reverted my commits.	2024-11-16 14:50:06 -06:00
Jordan Carlin	f6b0805fd4	More lint cleanup: remove unused params	2024-11-16 12:35:37 -08:00
Jacob Pease	dda3cd6bea	Removed unnecessary separate if statement.	2024-11-16 14:29:58 -06:00
David Harris	56cbcf222b	Merge pull request #1107 from jordancarlin/lint ... Clean up verilator lint off commands and remove unnecessay ones	2024-11-16 12:16:52 -08:00
Jacob Pease	2ee4525ba9	Made minor changes to the controller to clean up the logic. Still need to simplify the first always block.	2024-11-16 11:34:31 -06:00
Jordan Carlin	a462b9a2e6	Clean up verilator lint off commands and remove unnecessay ones	2024-11-15 23:52:50 -08:00
David Harris	234e47a7c5	MTIMECMP should reset to maximum value for RV32, not just for RV64	2024-11-15 15:37:25 -08:00
Vikram Krishna	0c0949e82b	added explanation	2024-11-14 03:54:32 -08:00
Vikram Krishna	eb777d3fa4	updated froundnx conditional	2024-11-14 03:53:26 -08:00
Vikram Krishna	4aecba2a51	added handling for OpCode=100	2024-11-14 03:51:27 -08:00
Rose Thompson	e22f30ec14	Better name for CacheSetTag2.	2024-11-13 12:24:35 -06:00
Rose Thompson	ef7072b7c2	Merge branch 'main' into lrufixes	2024-11-12 17:57:28 -06:00
Rose Thompson	383fce5522	Fixed the issue with cbo.clean.	2024-11-12 14:38:44 -06:00
Rose Thompson	b7b7c79726	CBO.FLUSH was not clearing the valid bit if the cacheline was clean.	2024-11-12 14:16:55 -06:00
Rose Thompson	8a4868ac57	Resolved a bug in the cache but there are still mismatches with the cache simulator.	2024-11-12 11:35:29 -06:00
Rose Thompson	3137fd7db2	Resolved some of the issues with the cache simulator mismatching with Wally. The LRU was incorrectly updating it's state while the cache was stalled causin g the LRU state to be update when it should not be.	2024-11-11 14:23:58 -06:00
naichewa	515e05ed75	Merge branch 'openhwgroup:main' into main	2024-11-08 11:07:29 -08:00
naichewa	396a17623b	Fixed TransmitStart resetting SCK and delay counter while already counting	2024-11-08 11:05:38 -08:00
Mike Kuskov	e57473ece1	Fix minor typos in src/fpu/postproc	2024-11-08 02:23:44 +03:00
naichewa	e59ca12cdc	Merge branch 'main' of https://github.com/naichewa/cvw	2024-11-07 12:14:28 -08:00
naichewa	987015a2a7	Fix SPI Delay1 behavior	2024-11-07 12:14:23 -08:00
naichewa	24509adea3	Merge branch 'openhwgroup:main' into main	2024-11-07 10:49:36 -08:00
naichewa	7964358651	Fix erroneous implicit sckcs and cssck phase delays	2024-11-07 10:47:51 -08:00
naichewa	7637f3e33b	Fix erroneous implicit sckcs and cssck phase delays	2024-11-07 10:19:55 -08:00
naichewa	927398a017	Fix SPI state skipping sck-cs delay when at end of transmission	2024-11-07 10:17:22 -08:00
Corey Hickson	1570a6338e	Fixed fmvp.d.x bug	2024-11-06 03:32:53 -08:00
Jacob Pease	507c1dad1c	Removed impossible condition in receive register logic.	2024-11-04 16:15:42 -06:00
Jacob Pease	120b21d7d5	More SPI optimizations.	2024-11-04 15:38:12 -06:00
Jacob Pease	745e53adf7	Merge branch 'main' of github.com:openhwgroup/cvw	2024-11-04 11:56:15 -06:00
Corey Hickson	0c6e9dc770	Fixed rmm rounding mode bug	2024-11-03 14:21:55 -08:00
Jacob Pease	a9e6962cd4	Removed unused signals and renamed other signals. Removed a bunch of delay counters and simply reuse one counter for all delay types. Tested on FPGA and it also passes regression.	2024-11-03 00:35:40 -05:00
Jacob Pease	674d008f23	Added headers to files.	2024-11-02 14:31:05 -05:00
Jacob Pease	c197d4a3c6	Cleaned up some code. Still more work to do there.	2024-11-01 17:35:55 -05:00
Jacob Pease	e881bd3120	Changed the condition for TransmitStart fsm to avoid edge condition.	2024-11-01 17:04:07 -05:00
Jacob Pease	eddae8e1a6	Fixed ShiftEdge and SampleEdge to not always include PhaseOneOffset. Before, it worked in simulation, but not on the FPGA.	2024-11-01 13:02:17 -05:00
Jacob Pease	56a6ad3376	Fixed lint issues.	2024-10-31 15:56:16 -05:00
Jacob Pease	3ee5fffe02	Fixing latches.	2024-10-31 13:54:56 -05:00
Jacob Pease	72a854eb07	Refactored SPI passes regression save for hardware interlock tests.	2024-10-31 13:01:25 -05:00