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818 Commits

Author SHA1 Message Date
Ross Thompson
ebe4339953 Updated fpga test bench. 
Solved read delay cache bug.  Introduced during cache optimizations.
 2022-08-21 15:59:54 -05:00
Ross Thompson
85dbec5969 Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation. 2022-08-21 15:28:29 -05:00
Ross Thompson
f3f0f12904 Removed logic from Verilog wrapper. 2022-08-21 14:07:43 -05:00
Katherine Parry
a191603a1a fixed -1 issue in division 2022-08-20 00:53:45 +00:00
Ross Thompson
2ba390adf4 Possible reduction of ignorerequest. 2022-08-19 18:07:44 -05:00
Ross Thompson
517c0f6c35 Changed signal names. 2022-08-17 16:12:04 -05:00
Ross Thompson
f6e5746e59 Better name for LSUBusWriteCrit. Changed to SelLSUBusWord. 2022-08-17 16:09:20 -05:00
Ross Thompson
299aefb76a Removed old code from interlockfsm. 2022-08-17 12:52:56 -05:00
Katherine Parry
9549c23f45 sqrt tests in regression uncommented and pass 2022-08-07 23:38:10 +00:00
Katherine Parry
cb0c1b7488 radix-2 1 copy passes testfloat 2022-08-06 22:54:05 +00:00
Katherine Parry
de6ae471bc fixed fsw problem and removed 2 bit shift from shift correction 2022-08-03 22:16:51 +00:00
David Harris
e70b28f7f6 FMA cleanup 2022-08-02 07:42:32 -07:00
David Harris
2b932c4b80 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-02 07:34:12 -07:00
David Harris
887e4c73fb Moved InvA to sign block; simplified fmaexpadd coding 2022-08-02 07:34:09 -07:00
Ross Thompson
413a9bf58b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-01 22:09:11 -05:00
Ross Thompson
57fcf0ef79 Fixed fstore2 in cache? 2022-08-01 22:04:44 -05:00
David Harris
06c4f18cd1 merged lza back into main 2022-08-01 19:45:21 -07:00
David Harris
8147f75399 Fixed fmaadd to work with new LZA 2022-08-01 19:40:55 -07:00
Ross Thompson
797d9e3610 Replaced swbytemask with swbytemaskword (1 liner). Credit to David Harris. 2022-08-01 21:12:25 -05:00
Ross Thompson
3cd8404917 Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask. 2022-08-01 21:08:14 -05:00
Ross Thompson
3612db2d70 pulled swbbytemask out of subword write. 2022-08-01 20:48:45 -05:00
David Harris
7e4b04ff64 Parameterized fmalza 2022-08-01 16:18:02 -07:00
David Harris
94fa7a00e7 Completed LZA simplificaiton 2022-08-01 16:13:16 -07:00
David Harris
3b937b73fd lza cleanup 2022-08-01 16:01:02 -07:00
David Harris
b614f165fb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-01 15:47:58 -07:00
David Harris
91597bba87 lza cleanup 2022-08-01 15:47:03 -07:00
David Harris
f56b26ec40 lza cleanup 2022-08-01 15:43:48 -07:00
David Harris
c3e9719c99 lza cleanup 2022-08-01 15:40:12 -07:00
David Harris
d6b5e7a6ef lza cleanup 2022-08-01 15:37:09 -07:00
Katherine Parry
8ff3a693af regression passes fpu tests 2022-08-01 19:56:25 +00:00
Katherine Parry
9c68f85822 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-01 19:55:50 +00:00
David Harris
2869d67e50 more lza cleanup 2022-08-01 12:34:00 -07:00
David Harris
b34d2065c3 LZA cleanup 2022-08-01 12:30:42 -07:00
David Harris
99462049e7 LZA refactoring switched to Pp1, Gm1, Km1 2022-08-01 12:20:23 -07:00
David Harris
3c08aabcd3 LZA refactoring 2022-08-01 11:36:21 -07:00
Katherine Parry
eddf6e9ee1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-01 18:35:07 +00:00
David Harris
7f9b601467 fmalza edits to match textbook 2022-08-01 18:23:39 +00:00
David Harris
257107f908 Partitioned fma into separate files 2022-08-01 18:07:38 +00:00
Ross Thompson
1ee613ae6c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-31 12:48:51 -05:00
Katherine Parry
1bd6351e1f re-added FStore2 in Cache 2022-07-29 22:54:49 +00:00
David Harris
93d7d7179e Added parity and stop bit tests to UART 2022-07-28 04:35:51 +00:00
Ross Thompson
40e7cda84a Don't use this commit yet. Untested. 2022-07-24 15:40:52 -05:00
Ross Thompson
719b00e338 Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested. 2022-07-24 01:20:29 -05:00
Ross Thompson
69d520a7eb Removed replay from the config files. 2022-07-24 00:34:11 -05:00
Ross Thompson
cd68896637 Merged evict dirty clear with flush write back. 2022-07-24 00:22:43 -05:00
Ross Thompson
8193946996 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-23 08:41:59 -05:00
Ross Thompson
05484c4c05 signal name cleanup. 2022-07-22 23:36:27 -05:00
Ross Thompson
27e32980ad cache cleanup after removing replay on cpubusy. 2022-07-22 23:30:25 -05:00
Ross Thompson
17ae1a1b1b cache fsm cleanup after removal of replay. 2022-07-22 23:25:09 -05:00
Ross Thompson
abc79c6c8e Possible improvement to cache which removes the cpu_busy states. 2022-07-22 23:20:37 -05:00
Katherine Parry
655e2d3810 merged radix-2 sqrt into divider - doesnt work yet 2022-07-23 00:41:18 +00:00
slmnemo
bfced6bfe8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-22 17:13:38 -07:00
slmnemo
ca4511b6dc Fixed UART FIFO bugs and added FIFO tests 2022-07-22 17:13:19 -07:00
Katherine Parry
b3d932cd61 divider sizes reworked to match book 2022-07-22 22:02:04 +00:00
David Harris
d22587090b Reset MSR on read 2022-07-22 04:29:27 +00:00
slmnemo
3d2c6683d8 Fixed UART bug related to parity and MSR/LSR 2022-07-21 20:35:46 -07:00
Katherine Parry
fbe8bb2298 radix-4 division integrated into srt - not tested 2022-07-21 19:38:06 +00:00
Katherine Parry
7950a675ea added input enables and improved forwarding 2022-07-21 01:20:06 +00:00
Katherine Parry
a30d9c6bd8 turn off 2 word store durring non-fp instructions 2022-07-20 21:57:23 +00:00
Ross Thompson
1cad05fef9 Minor cleanup of cache. 2022-07-19 23:04:23 -05:00
Ross Thompson
8698799077 Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction. 2022-07-19 22:42:25 -05:00
Katherine Parry
b26297e874 moved ctrl signal registers into fctrl, also a lot of code cleaning 2022-07-20 02:27:39 +00:00
cturek
0f94177765 small changes 2022-07-20 01:36:25 +00:00
Katherine Parry
d61f84e751 oprimized zeros and replaced complex ?: with always_comb 2022-07-19 23:44:37 +00:00
Ross Thompson
a79e5e11f6 Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added. 2022-07-18 23:37:18 -05:00
Katherine Parry
514674417e moved Se into execute stage 2022-07-19 01:10:10 +00:00
Katherine Parry
64b3e4117b reworked fmashiftcalc to match book 2022-07-19 00:04:24 +00:00
David Harris
9fd772ce83 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-18 23:11:12 +00:00
Katherine Parry
cce5fb8dfd moved Ss to execute stage 2022-07-18 20:48:56 +00:00
Katherine Parry
7268b4b334 removed underflow from inexactct calculation 2022-07-18 17:51:18 +00:00
Katherine Parry
d6f1fc12db Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-18 17:31:29 +00:00
Katherine Parry
0210718f19 renamed signals in ocde to match book 2022-07-18 17:31:17 +00:00
Ross Thompson
0ef6137ab9 Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN. 2022-07-17 21:05:31 -05:00
Ross Thompson
8356e5d742 Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width. 2022-07-17 16:20:04 -05:00
David Harris
03f573351a Rewrote convert shift calculation with always for ease of reading 2022-07-17 16:40:58 +00:00
David Harris
622773343f restored intPending logic to be sticky for PLIC 2022-07-16 17:43:31 -07:00
Katherine Parry
e3ed40620c forgot some files 2022-07-15 21:42:45 +00:00
Katherine Parry
5cb9c9f319 merged floating-point radix-2 divider with radix-4 2022-07-15 20:16:59 +00:00
Katherine Parry
2fe8b6e34c fixed error in divsqrt 2022-07-14 18:16:00 +00:00
Katherine Parry
66bef379cb renamed a file to fit diagram 2022-07-13 23:44:54 +00:00
Katherine Parry
3dcddf8453 some code cleanup 2022-07-13 15:28:22 -07:00
Katherine Parry
b874c5c05d removed minus 1 case in rounding 2022-07-13 15:01:38 -07:00
Katherine Parry
b45b3baec2 removed the +1 in the cvt 2022-07-13 09:41:35 -07:00
Katherine Parry
3c1bea1104 removed warnings and took a mux out of the critical path 2022-07-12 18:32:17 -07:00
Katherine Parry
12a54161c0 found the bug in the store modification 2022-07-12 22:42:19 +00:00
Katherine Parry
18d7fee541 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
Katherine Parry
1267d33d3c forgot a file 2022-07-11 18:31:51 -07:00
Katherine Parry
ba339fc794 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-11 18:30:29 -07:00
Katherine Parry
bea4ec078d variable interations implemented in radix-4 divider 2022-07-11 18:30:21 -07:00
David Harris
03a20610aa added comment about checking SRAM size 2022-07-10 12:48:51 +00:00
David Harris
d1a7832dd9 added comment about RAMs in cacheway 2022-07-10 12:47:34 +00:00
Katherine Parry
62205ebb3b renamed FLoad2 to FStore2 2022-07-09 00:26:45 +00:00
Katherine Parry
97e7e619d9 moved fpu ieu write data mux to lsu 2022-07-08 23:56:57 +00:00
Katherine Parry
c56fdd7e0f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-08 12:30:50 -07:00
Katherine Parry
88b4f9b40a renamed signals in cvt and prostproc 2022-07-08 12:30:43 -07:00
James Stine
99fed5d59f Update SRAM to /proj/wally 2022-07-08 08:09:55 -05:00
David Harris
87ea95e6c5 erge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-08 09:09:07 +00:00
David Harris
5ae88dbef0 Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc 2022-07-08 09:09:02 +00:00
David Harris
96cc66d151 Adjusting byte writes to RAM 2022-07-08 08:45:21 +00:00
David Harris
38ef8eebbb Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables 2022-07-08 08:44:37 +00:00
David Harris
234175f236 Removed unused swbytemask from CLINT 2022-07-08 08:43:24 +00:00
Katherine Parry
b67792086c moved unsused division code again 2022-07-07 16:41:26 -07:00
Katherine Parry
b1e2a1e5a1 Revert "moved old divsqrt to unusedsrc" 
This reverts commit 5dd07c76bd.
 2022-07-07 16:29:17 -07:00
Katherine Parry
5dd07c76bd moved old divsqrt to unusedsrc 2022-07-07 16:09:56 -07:00
Katherine Parry
75a8cea4e4 srt divider merged into fpu 2022-07-07 16:01:33 -07:00
David Harris
425fec0f41 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-07 22:00:59 +00:00
Katherine Parry
c581fba4aa modified wally shared 2022-07-07 21:59:43 +00:00
David Harris
f865994ba1 fixing port errors 2022-07-07 21:57:10 +00:00
Katherine Parry
7771f7b3eb added load and store test 2022-07-07 21:48:51 +00:00
David Harris
f2915129ab Preliminary SRAM integration 2022-07-07 19:56:20 +00:00
David Harris
21fb120aac Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-06 23:43:05 +00:00
Ross Thompson
d716c25275 Fixed an issue with direct map cache's nextway logic. 
Also found a small error in the replacement policy.
 2022-07-06 18:34:30 -05:00
Madeleine Masser-Frye
ad29e19a27 fixed width mismatch for rv64 ieuadrM and readdatawordM 2022-07-06 22:39:35 +00:00
David Harris
529f48ed58 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-06 13:26:26 +00:00
David Harris
76302a8599 PLIC and UART passing tests on APB 2022-07-06 13:26:14 +00:00
Madeleine Masser-Frye
52562c9190 new priority onehot module for better area/time 2022-07-06 00:08:59 +00:00
Madeleine Masser-Frye
b5454f3a55 took first match out of pmpadrdec 2022-07-06 00:02:01 +00:00
Madeleine Masser-Frye
d8ea12c6f4 fixed concatenation syntax 2022-07-05 22:36:54 +00:00
David Harris
72e216d053 APB CLINT passing regression 2022-07-05 15:51:35 +00:00
David Harris
5f5ad77d4a Modified uncore to use AHB bridge to GPIO 2022-07-05 05:02:21 +00:00
David Harris
c8ac05ba7b AHB bridge for gpio 2022-07-05 05:01:59 +00:00
David Harris
ca95b46de5 Added reference to Schmookler01 for LOA 2022-07-05 05:01:12 +00:00
David Harris
1a356312b2 Added comments to PLIC about likely bug 2022-07-05 05:00:29 +00:00
David Harris
abfd935e06 removed delay in ahblite 2022-07-05 04:59:28 +00:00
Katherine Parry
2fc795ca70 added missing files 2022-07-03 21:40:47 -07:00
Katherine Parry
8ac722f693 Renaming signals to match chapter 2022-07-03 12:26:22 -07:00
David Harris
0fa35acbc5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-02 19:37:14 +00:00
David Harris
89b319aa1b FMA ZAligned name 2022-07-02 19:35:13 +00:00
Katherine Parry
8930cdcfbb some prostprocessing cleanup 2022-07-01 14:55:46 -07:00
Katherine Parry
8f98f3bfab added rv32 double precision stores - untested 2022-06-28 21:33:31 +00:00
Katherine Parry
0417a6a45b very basic early termination passes testfloat 64-bit tests 2022-06-28 00:16:22 +00:00
Katherine Parry
a5fb60eb1a radix-4 early termination working for special cases - not working completely 2022-06-27 20:43:55 +00:00
Katherine Parry
adaee899bb radix-4 divider passing all double precision testfloat tests 2022-06-27 17:04:51 +00:00
Katherine Parry
70a1bb8377 fixed commented out error and removed killprod from result selection 2022-06-25 01:42:23 +00:00
Katherine Parry
fa1623551c passing regression again 2022-06-25 00:31:32 +00:00
Katherine Parry
6d6cc7bb48 commented out error - also some divider bugs fixed 2022-06-25 00:04:53 +00:00
Katherine Parry
43882d5878 modified result select to account for x/inf 2022-06-24 21:23:15 +00:00
Katherine Parry
a85a868b56 radix 4 division denormal result handeling 2022-06-24 21:02:50 +00:00
Katherine Parry
9eefba5b58 added denormal input handeling - radix 4 2022-06-24 19:41:40 +00:00
Katherine Parry
ff1fae74d8 division by zero added 2022-06-24 01:09:44 +00:00
Katherine Parry
ec2c446c7e forgot a file 2022-06-23 23:01:30 +00:00
Katherine Parry
b16e55906a div debug - accounted for 1 bit normalization in exponent calculation 2022-06-23 22:59:43 +00:00
Katherine Parry
749d405da8 lint warning fix 2022-06-23 22:37:44 +00:00
Katherine Parry
de71773d69 added radix-4 0/d handling 2022-06-23 22:36:19 +00:00
slmnemo
bca8fe1694 Removed big64.txt reference, fixing a warning 2022-06-23 14:39:53 -07:00
David Harris
44216b3967 Fixed typo in clint 2022-06-23 21:27:46 +00:00
David Harris
d969edeb99 Reset mtimecmp in clint 2022-06-23 21:20:55 +00:00
Katherine Parry
d7a363aaa7 fixt lint error 2022-06-23 16:11:50 +00:00
Katherine Parry
1612daa294 Testfloat running division - not passing 2022-06-23 00:07:34 +00:00
Madeleine Masser-Frye
6229779b97 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-21 20:31:06 +00:00