Ross Thompson
f1f7884e10
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-10 15:37:02 -06:00
Ross Thompson
149c9aa0f2
Added debug option to disable the function radix if not needed.
...
Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
2021-03-10 15:17:02 -06:00
Ross Thompson
4d7e926dbb
I finally think I got the function radix debugger working across both 32 and 64 bit applications.
2021-03-10 14:43:44 -06:00
Noah Boorstin
2d1f63b590
change flop in ahb controller to use normal flop module
2021-03-10 19:14:02 +00:00
Ross Thompson
7b7cacbaf0
Finally I think I have the function radix mapping across all applications correctly. I still need to clean up the code a bit so it is easier to understand.
2021-03-10 11:00:51 -06:00
David Harris
0baa004bb4
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-09 09:28:32 -05:00
David Harris
bea8ac6d59
WALLY-LRSC atomic test passing
2021-03-09 09:28:25 -05:00
Noah Boorstin
87e2a9b920
busybear: better NOPing out of float instructions
2021-03-08 21:24:19 +00:00
Noah Boorstin
9274d09ae2
busybear: better instrF checking
...
So this now checks instrF only when StallD is low. @kaveh I'd love your
opinion on this. I don't know if this is a good idea or not. Ideally we
should probably be checking InstrRawD instead, but I kind of want to stay
checking the instr in the F stage instead of D for now. Idk if this is worth
staying in F, I can't really see any big downsides to checking the instruction in
D except that PCD isn't an external signal, but neither is StallD, so.....
Anyway I'd love others' thoughts on this
2021-03-08 19:48:12 +00:00
Noah Boorstin
08e3691e59
busybear: make a second .do file with better optimization for command line mode
2021-03-08 19:35:00 +00:00
Noah Boorstin
1fc00d41c2
busybear: load mem files from verilog instead of .do
2021-03-08 19:26:26 +00:00
David Harris
52d4a04eb0
Created atomic test vector and directories
2021-03-08 09:38:55 -05:00
Ross Thompson
a3759f585d
Updated the paths to the branch predictor memory preloads for busy bear.
2021-03-05 15:36:00 -06:00
Ross Thompson
d6bc34121f
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-05 15:27:22 -06:00
Ross Thompson
9a93193d6a
Oups. I forgot to update other do files with the commands to preload the branch predictor memories.
2021-03-05 15:23:53 -06:00
Noah Boorstin
d3bf36b15f
busybear: add branch preditor loading to do file
...
(sorry to add more loading to the do instead of less)
2021-03-05 21:01:41 +00:00
Noah Boorstin
f0a103687e
Merge branch 'main' into busybear
2021-03-05 20:27:19 +00:00
Noah Boorstin
6981907521
fix wally-pipelined-batch.do to match wally-pipelined.do
2021-03-05 20:27:01 +00:00
bbracker
612f7a9ee4
added a delay to sel signals
2021-03-05 15:07:34 -05:00
bbracker
a1223ee13b
more merging fixes
2021-03-05 14:36:07 -05:00
bbracker
2cd0f19129
remove deprecated mem signals
2021-03-05 14:27:38 -05:00
bbracker
420c9a11c2
refactored sim file
2021-03-05 14:25:16 -05:00
bbracker
62dd9e3075
first merge of ahb fix
2021-03-05 14:24:22 -05:00
Noah Boorstin
464c1de03d
busybear: slight testbench update
2021-03-05 19:00:40 +00:00
Noah Boorstin
0af002eb2f
busybear: make CSRs only weird for us
2021-03-05 00:46:32 +00:00
Noah Boorstin
7208b9bcf2
busybear: better implenetation of sim-busybear-batch
2021-03-05 00:39:03 +00:00
Ross Thompson
a982ad7a9a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-04 17:31:27 -06:00
Ross Thompson
7902c3fdb6
updated the function radix to look at wally signals.
2021-03-04 17:31:12 -06:00
Noah Boorstin
cfcd7d1518
busybear: make imperas tests work again
2021-03-04 22:44:49 +00:00
Katherine Parry
5374dca1b9
fixed various bugs
2021-03-04 22:20:39 +00:00
Katherine Parry
4591b25c86
fixed various bugs
2021-03-04 22:20:28 +00:00
Katherine Parry
6fa2bc8efe
fixed various bugs
2021-03-04 22:20:23 +00:00
Katherine Parry
10b179399c
fixed various bugs
2021-03-04 22:20:02 +00:00
Katherine Parry
8e3b74c772
fixed various bugs
2021-03-04 22:19:21 +00:00
Katherine Parry
4e6b35c8b2
fixed various bugs
2021-03-04 22:18:47 +00:00
Katherine Parry
3c86d0912a
fixed various bugs
2021-03-04 22:18:19 +00:00
Ross Thompson
5b7f0772ca
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-04 16:06:22 -06:00
Brett Mathis
b5a08e496f
Pipelined functional units for FPU
2021-03-04 14:30:11 -06:00
Noah Boorstin
5c456e2d7f
busybear: comment out instraccessfaultf for imem for now
2021-03-04 20:26:41 +00:00
Noah Boorstin
fde94f9057
Merge branch 'main' into busybear
...
Conflicts:
wally-pipelined/src/uncore/imem.sv
2021-03-04 20:16:03 +00:00
Ross Thompson
619bbd9d83
Merge branch 'bp' into main
...
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
Ross Thompson
a8cd4f2b2e
Fixed forwarding around the 2 bit predictor.
2021-03-04 13:01:41 -06:00
bbracker
7852d866ef
JALR testing
2021-03-04 10:37:30 -05:00
bbracker
5de23fcbe0
changed test maker to output trace files for debug
2021-03-04 10:36:04 -05:00
Ross Thompson
d0223da2f7
Converted to using the BTB to predict the instruction class.
2021-03-04 09:23:35 -06:00
Thomas Fleming
8c410b6fbe
Install dtlb in dmem
2021-03-04 03:30:06 -05:00
Thomas Fleming
1a2db17ee5
Install tlb into ifu
2021-03-04 03:11:34 -05:00
Thomas Fleming
ab6ae6d3f1
Merge branch 'tlb_toy' into main
2021-03-04 02:41:11 -05:00
Thomas Fleming
7a9f866120
Move tlb into mmu directory
2021-03-04 02:39:08 -05:00
Teo Ene
b15ef47d24
Fix to 32-bit option of commit 2d40898158
2021-03-04 01:33:34 -06:00
