Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-23 13:04:28 +00:00
Code Issues Packages Projects Releases Wiki Activity
Configurable RISC-V Processor
295 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.8%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
a3759f585d
Go to file
Ross Thompson a3759f585d Updated the paths to the branch predictor memory preloads for busy bear.
2021-03-05 15:36:00 -06:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
wally-pipelined Updated the paths to the branch predictor memory preloads for busy bear. 2021-03-05 15:36:00 -06:00
.gitignore add .nfs* files to gitignore 2021-02-28 20:48:01 +00:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor