David Harris
32c102d89a
All deriv tests generated, use sim/make deriv
2024-01-29 14:34:42 -08:00
David Harris
d52d2d7983
Initial derivgen working
2024-01-29 11:22:34 -08:00
David Harris
45e2317636
Added Wally github address to header comments
2024-01-29 05:38:11 -08:00
David Harris
7215f48dda
coverage improvements: fixing problems running ImperasDV on coverage tests
2024-01-23 22:21:01 -08:00
David Harris
d801bf5d6c
Revert "more shiftcorrection bug fixes"
2024-01-21 10:41:14 -08:00
Kevin Kim
1459943a75
more shiftcorrection bug fixes
2024-01-21 10:08:48 -08:00
Kevin Kim
991f1494d3
Merge branch 'openhwgroup:main' into shiftcorrectiondebug
2024-01-21 08:27:33 -08:00
Kevin Kim
3241802441
fixed bug in CORRSHIFTSZ param
2024-01-21 08:25:17 -08:00
David Harris
9260d3c424
Add Zfh support to imperas.ic, use Zicond in riscof now that it is fixed in riscv-arch-test
2024-01-18 22:46:07 -08:00
David Harris
17c9be7695
Cleanup typos, remove Zicond from riscof until it is working
2024-01-18 21:36:52 -08:00
David Harris
60e09965d5
Enabled Zfh support in rv64gc
2024-01-16 11:14:43 -08:00
David Harris
bb3a7850c4
Simplified floating-point parameters in config-shared
2024-01-15 17:48:41 -08:00
David Harris
da4eca4854
Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int.
2024-01-15 13:24:57 -08:00
Rose Thompson
ba95e5fafd
Reduced the rv64gc config to 128MiB memory.
2024-01-12 20:01:05 -06:00
David Harris
9eb6d9c8b8
Added Zicond support
2024-01-11 07:37:15 -08:00
David Harris
dc3284049c
Rolled back B extension in rv32/64gc MISA because imperasDV isn't matching
2023-12-21 11:03:50 -08:00
David Harris
09ea6e6485
Set B in MISA for rv32gc and rv64gc
2023-12-20 16:29:31 -08:00
Rose Thompson
5062a8c89c
Added parameter for cache's SRAM length.
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Progress towards verilator support.
2023-12-18 12:50:49 -06:00
Rose Thompson
b02bd6c835
Finally we got the wally tracer working with linux.
2023-11-21 13:45:55 -06:00
Rose Thompson
b137759b45
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-11-20 10:34:36 -06:00
Rose Thompson
3594c08d4b
Modified linux imperas tests to
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1. enable zicclsm
2. enable logging at 7000 ms
2023-11-20 10:30:35 -06:00
David Harris
b692c913c4
Changed rv32gc to do IDIV in MDU and have k=2 copies of FDIV stages; added correct sky130 adder data; fixed feature substitution in synthesis makefile
2023-11-18 20:56:50 -08:00
David Harris
acc2db256f
turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep
2023-11-17 20:25:24 -08:00
David Harris
96556064a4
Restored RV64GC BPRED_SIZE=10 for consistent synthesis results
2023-11-17 18:31:44 -08:00
David Harris
fb135c957c
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-11-14 15:19:22 -08:00
David Harris
5e9157244b
Restored Zfh to 0 for rv64gc because it breaks floating-point tests
2023-11-14 15:18:16 -08:00
Rose Thompson
bf51948616
Merge pull request #474 from davidharrishmc/dev
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FP and synthesis cleanup
2023-11-14 12:03:01 -08:00
David Harris
8ba0336c6f
Removed unused addins, cleaned up configuration to support half precision on RV64gc, gate unused hazard inputs to reduce critical path in rv32e
2023-11-14 11:01:58 -08:00
David Harris
5211b3aa85
Merge pull request #473 from ross144/main
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Missed a few files in the last pull request. Removes the fpga config from the linter.
2023-11-14 10:15:31 -08:00
Rose Thompson
fdb75203cb
Added cbop to to rv32gc.
2023-11-14 10:55:22 -06:00
David Harris
a77bea9954
Merge pull request #472 from ross144/main
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Merge Zicclsm into main branch and removes the FPGA config. FPGA makefile now automatically creates the config when building
2023-11-14 08:34:06 -08:00
Rose Thompson
05eb5460b4
Removed fpga config. No longer needed.
2023-11-13 17:50:29 -06:00
Rose Thompson
95fc5f4a1c
Towards removing the FPGA config file.
2023-11-13 17:20:26 -06:00
David Harris
571c7d3be4
Divider cleanup
2023-11-12 19:41:12 -08:00
David Harris
f437336540
Explained sqrt preshifting
2023-11-12 10:05:54 -08:00
David Harris
6ac83c776e
Cleaned up number of bits in fdivsqrt
2023-11-11 15:50:06 -08:00
David Harris
2bf5143163
Bug fixes related to size of fpdivsqrt bit count and number of cycles
2023-11-11 05:58:53 -08:00
David Harris
448ced00c5
Fixed testbench-fp to reflect signal name changes
2023-11-11 04:05:34 -08:00
David Harris
d5ba8fc5e6
fdivsqrt parameter cleanup
2023-11-10 18:33:08 -08:00
David Harris
3cae2385ab
Simplified out LOGRK parameter
2023-11-10 18:19:41 -08:00
Rose Thompson
b74bfbeefd
Merge branch 'main' into Zicclsm
2023-11-10 16:15:32 -06:00
David Harris
953c53d065
fdivsqrt parameter cleanup
2023-11-10 09:11:15 -08:00
David Harris
4c106215f4
Started cleaning up shifting leading 1 in fdivsqrt
2023-11-10 08:46:55 -08:00
Rose Thompson
0a4ed5515b
Merge branch 'main' into Zicclsm
2023-11-02 12:55:51 -05:00
Rose Thompson
7222aaa196
Enabled Zicclsm in rv64gc.
2023-11-02 12:47:40 -05:00
naichewa
e3d8162279
harris code review 3
2023-11-01 10:14:15 -07:00
naichewa
7dd3f24d6c
Merge branch 'main' into spi
2023-10-30 17:01:41 -07:00
David Harris
f6a7f707bd
Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
2023-10-30 09:56:17 -07:00
Rose Thompson
657409aec5
Addec ZICCLSM to config files and started on lsu instance.
2023-10-27 13:07:23 -05:00
David Harris
b76c371e45
Config file cleanup
2023-10-18 05:38:36 -07:00
naichewa
0ff9ce527d
Merge branch 'main' into spi
2023-10-16 22:59:50 -07:00
David Harris
1a6e57f8c0
Renamed wally-config to config in many comments
2023-10-16 13:49:09 -07:00
naichewa
d5d4f9d044
transferred spi changes in ECA-authorized commit
2023-10-12 13:36:57 -07:00
David Harris
28752303be
Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there
2023-10-04 12:28:12 -07:00
Ross Thompson
f863cbf366
Actually fixed non-power of 2 issue with RAS.
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Added RAS swapping to branch predictor scripts and configurations.
2023-09-27 12:25:05 -05:00
Ross Thompson
95c653e7df
Fixes the bpred-sim.py to support command line parameterization of the branch predictor while using the new parameterization. This is definitely a hack, but I don't see a better way.
2023-09-15 14:05:26 -05:00
Kevin Kim
dabd15e029
synth works
2023-08-26 21:11:21 -07:00
David Harris
7a092a2275
Fixed merge conflict for ZICBOP
2023-08-25 18:41:57 -07:00
David Harris
f7b50f4721
Preparing to merge with CBO* changes
2023-08-25 18:41:03 -07:00
David Harris
c6631ef808
Added N and PBMT bits to MMU PTE
2023-08-24 19:44:46 -07:00
Ross Thompson
914b6f9734
Now have CBOZ instructions working!
2023-08-24 16:47:35 -05:00
Ross Thompson
0662df511d
Modified rv32gc and rv64gc configs to enabled Zicbom.
2023-08-21 13:48:20 -05:00
David Harris
d58ece3d44
renamed test-shared.vh to config-shared.vh
2023-07-30 05:22:39 -07:00
Ross Thompson
dbf9e5da0b
Updated Arty A7 fpga config and device tree to 256MiB main memory.
2023-07-25 15:11:47 -05:00
Ross Thompson
0ae9e8bfde
Removed old sdc from all configs.
2023-07-24 15:55:22 -05:00
Ross Thompson
b1f7a5768f
Removed all old references to the old flash card controller.
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Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
2023-07-24 15:45:57 -05:00
Ross Thompson
63afd95ad3
Fixed bugs in boot and new flash card merge. Works with arty a7 now.
2023-07-22 15:52:25 -05:00
Ross Thompson
a89a1e675c
Merge branch 'boot' into mergeBoot
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Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Ross Thompson
e4d6a9f8c6
Removed all old configuration files.
2023-07-19 10:28:54 -05:00
Ross Thompson
af0e33209f
Removed QEMU from configurations.
2023-07-19 10:23:55 -05:00
Ross Thompson
b756b248b4
Wow. The newest version of Vivado does not like the enums as parameters.
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The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
2023-07-18 15:07:10 -05:00
Jacob Pease
b3aaa87cba
Modified bootloader to access GUID partitions. SDC interrupt to PLIC.
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Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.
The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself was modified to accept the
SDC interrupt signal.
2023-07-14 13:36:44 -05:00
David Harris
644afa16cd
Clean up privilege rs1 decoding and implement svinval as sfence.vma
2023-07-13 02:41:17 -07:00
Ross Thompson
cb22463763
Fixed slight bug in config from parameterization.
2023-07-07 16:33:34 -05:00
Ross Thompson
7aecd72c35
Fpga does not correctly boot linux. I think the solution here is to revert out all substantive changes except for parameterization and then add them back in one at a time. This is necessary because the parameterization is not completed in one contiguous group of commits.
2023-06-22 12:55:49 -05:00
Ross Thompson
85567841eb
Merge branch 'testbench-params2'
2023-06-15 15:31:13 -05:00
Ross Thompson
d2219023c3
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-06-15 14:57:23 -05:00
Ross Thompson
87fb9a3e16
Deleted remaining old configs except fpga as I still need to create the parameterized version.
2023-06-15 14:08:13 -05:00
Ross Thompson
75b5c23edd
Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems.
2023-06-15 14:05:44 -05:00
Ross Thompson
e27dfb8ce0
Merge branch 'verilator'
2023-06-11 15:28:04 -05:00
Ross Thompson
c7536663c0
Merge pull request #319 from davidharrishmc/dev
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Renamed Performance Counter extension
2023-06-09 21:21:45 -04:00
David Harris
b70b0c7c5e
Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare
2023-06-09 14:40:01 -07:00
David Harris
6a0d818d74
Other Wally cleanup
2023-06-09 09:37:09 -07:00
David Harris
df96900aa1
Added named support for Zicntr and Zihpm
2023-06-09 09:35:51 -07:00
Ross Thompson
a8a8422557
Updated parameterization types. Modelsim version 2022.1 did requires defaults to a 32 bit integer. The base and ranges for the address decoder need to be larger.
2023-06-09 09:28:24 -05:00
Ross Thompson
1ceea51d8b
Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet.
2023-05-31 16:51:00 -05:00
Ross Thompson
a963f0af3a
Updated source code to be compatible with verilator 5.011 for lint only.
2023-05-31 10:44:23 -05:00
Ross Thompson
1315a0bf4a
Got the branch predictor parameterized using Lim's method. Also had to add a global enum included in both cvw.sv and the configs which defines the branch predictor types. This should be synthesizable, but I'll need to double check.
2023-05-26 16:00:14 -05:00
Jacob Pease
40f81d5da6
The Vivado-RISC-V SDC works. Wally is now booting through it.
2023-05-26 15:42:33 -05:00
Ross Thompson
0020d94b39
Updated mmu's tlb and hptw to use Lim's parameterization.
2023-05-24 18:02:22 -05:00
Ross Thompson
b91b54589e
Updated a large number of the source files to use parameters rather than `defines. Based on Lim's work. So far there is no simulation slow down.
2023-05-24 14:05:44 -05:00
Ross Thompson
930fb67308
Trying to figure out why the parameterization slowed down modelsim so much.
2023-05-24 12:44:42 -05:00
Ross Thompson
69a9bf7055
Adds local history predictor.
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Fixes performance counters, but not coremark.
2023-05-23 18:53:46 -05:00
Ross Thompson
664231c0da
Merge branch 'localhistory'
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Repair to wave file.
Created implementations of local history. Part of my Ph.D. research.
2023-05-22 10:13:31 -05:00
David Harris
1b385c4336
Changed DIVN comparison from NF to NF+2. Shouldn't make a difference on our word sizes of XLEN=32/64, NF = 10/23/52) but is more proper in the general case.
2023-05-15 03:51:59 -07:00
Ross Thompson
d545a2ec74
Partially working local history repair.
2023-05-11 14:56:26 -05:00
Ross Thompson
414c79b923
Updated configs for local branch history `defines.
2023-05-02 11:11:04 -05:00
Kip Macsai-Goren
4aed880757
enabled SVADU for rv32/64gc
2023-04-11 17:42:26 -07:00
eroom1966
1a10e48ecf
update to allow running of ImperasDV with linux boot
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optimize performance of the tracer
2023-03-27 09:46:16 +01:00
kipmacsaigoren
2337e2ae16
Merge branch 'openhwgroup:main' into bit-manip
2023-03-07 21:29:03 -08:00
