mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-02 17:55:19 +00:00
All deriv tests generated, use sim/make deriv
This commit is contained in:
David Harris
parent
d52d2d7983
commit
32c102d89a
@ -34,6 +34,7 @@
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use strict;
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use warnings;
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import os;
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use Data::Dumper;
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my $curderiv = "";
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my @derivlist = ();
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@ -61,7 +62,8 @@ foreach my $line (<$fh>) {
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@derivlist = @{$inherits};
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}
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} else { # add to the current derivative
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my @entry = ($tokens[0], $tokens[1]);
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$line =~ /\s*(\S+)\s*(.*)/;
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my @entry = ($1, $2);
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push(@derivlist, \@entry);
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}
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}
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@ -79,21 +81,30 @@ foreach my $key (keys %derivs) {
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open(my $fh, '>>', $config) or die "Could not open file '$config' $!";
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my $datestring = localtime();
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my %hit = ();
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print $fh "// Config $key automatically derived from $basederiv{$key} on $datestring usubg derivgen.pl\n";
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foreach my $line (<$unmod>) {
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foreach my $entry (@{$derivs{$key}}) {
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my @ent = @{$entry};
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my $param = $ent[0];
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my $value = $ent[1];
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if ($line =~ s/$param\s*=\s*.*;/$param = $value;/g) {
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print("Hit: new line in $config is $line");
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#print $fh $line;
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if ($line =~ s/$param\s*=\s*.*;/$param = $value;/) {
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$hit{$param} = 1;
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# print("Hit: new line in $config for $param is $line");
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}
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}
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print $fh $line;
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}
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close($fh);
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close($unmod);
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foreach my $entry (@{$derivs{$key}}) {
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my @ent = @{$entry};
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my $param = $ent[0];
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if (!exists($hit{$param})) {
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print("Unable to find $param in $key\n");
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}
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}
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system("rm -f $dir/config_unmod.vh");
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}
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sub terminateDeriv {
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@ -153,7 +153,7 @@ localparam BPRED_SIZE = 32'd10;
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localparam BPRED_NUM_LHR = 32'd6;
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localparam BTB_SIZE = 32'd10;
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localparam RAS_SIZE = 32'd16;
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localparam ICLASSPRED = 1;
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localparam SVADU_SUPPORTED = 1;
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localparam ZMMUL_SUPPORTED = 0;
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@ -41,7 +41,7 @@ RESET_VECTOR 64'h1000
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UNCORE_RAM_RANGE 64'h0FFFFFFF
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UNCORE_RAM_PRELOAD 1
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GPIO_LOOPBACK_TEST 0
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SPI_LOOBACK_TEST 0
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SPI_LOOPBACK_TEST 0
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UART_PRESCALE 0
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PLIC_NUM_SRC 32'd53
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@ -63,7 +63,6 @@ DTIM_RANGE 32'h1FF
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IROM_RANGE 32'h1FF
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BOOTROM_RANGE 32'h1FF
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UNCORE_RAM_RANGE 32'h1FF
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BOOTROM_RANGE 32'h1FF
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WAYSIZEINBYTES 32'd512
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NUMWAYS 32'd1
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BPRED_SIZE 32'd5
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@ -76,3 +75,441 @@ deriv syn_rv32gc rv32gc syn_rv32e
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deriv syn_rv64i rv64i syn_rv32e
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deriv syn_rv64gc rv64gc syn_rv32e
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# The syn_sram configurations use SRAM macros
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deriv syn_sram_rv32e rv32e
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DTIM_RANGE 32'h1FF
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IROM_RANGE 32'h1FF
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USE_SRAM 1
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# The other syn configurations have the same trimming
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deriv syn_sram_rv32i rv32i syn_sram_rv32e
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deriv syn_sram_rv32imc rv32imc syn_sram_rv32e
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deriv syn_sram_rv32gc rv32gc syn_sram_rv32e
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deriv syn_sram_rv64i rv64i syn_sram_rv32e
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deriv syn_sram_rv64gc rv64gc syn_sram_rv32e
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# The following syn configurations gradually turn off features
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deriv syn_pmp0_rv64gc rv64gc syn_rv64gc
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PMP_ENTRIES 0
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deriv syn_sram_pmp0_rv64gc rv64gc syn_sram_rv64gc
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PMP_ENTRIES 0
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deriv syn_noPriv_rv64gc rv64gc syn_pmp0_rv64gc
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ZICSR_SUPPORTED 0
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deriv syn_sram_noPriv_rv64gc rv64gc syn_sram_pmp0_rv64gc
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ZICSR_SUPPORTED 0
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deriv syn_noFPU_rv64gc rv64gc syn_noPriv_rv64gc
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MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
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deriv syn_sram_noFPU_rv64gc rv64gc syn_sram_noPriv_rv64gc
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MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
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deriv syn_noMulDiv_rv64gc rv64gc syn_noFPU_rv64gc
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MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0)
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deriv syn_sram_noMulDiv_rv64gc rv64gc syn_sram_noFPU_rv64gc
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MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0)
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deriv syn_noAtomic_rv64gc rv64gc syn_noMulDiv_rv64gc
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MISA (32'h00000104 | 1 << 18 | 1 << 20)
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deriv syn_sram_noAtomic_rv64gc rv64gc syn_sram_noMulDiv_rv64gc
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MISA (32'h00000104 | 1 << 18 | 1 << 20)
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# Divider variants to check logical correctness
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deriv div_2_1_rv32gc rv32gc
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RADIX 32'd2
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DIVCOPIES 32'd1
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deriv div_2_2_rv32gc rv32gc
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RADIX 32'd2
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DIVCOPIES 32'd2
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deriv div_2_4_rv32gc rv32gc
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RADIX 32'd2
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DIVCOPIES 32'd4
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deriv div_4_1_rv32gc rv32gc
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RADIX 32'd4
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DIVCOPIES 32'd1
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deriv div_4_2_rv32gc rv32gc
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RADIX 32'd4
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DIVCOPIES 32'd2
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deriv div_4_4_rv32gc rv32gc
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RADIX 32'd4
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DIVCOPIES 32'd4
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deriv div_2_1i_rv32gc rv32gc div_2_1_rv32gc
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IDIV_ON_FPU 1
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deriv div_2_2i_rv32gc rv32gc div_2_2_rv32gc
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IDIV_ON_FPU 1
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deriv div_2_4i_rv32gc rv32gc div_2_4_rv32gc
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IDIV_ON_FPU 1
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deriv div_4_1i_rv32gc rv32gc div_4_1_rv32gc
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IDIV_ON_FPU 1
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deriv div_4_2i_rv32gc rv32gc div_4_2_rv32gc
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IDIV_ON_FPU 1
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deriv div_4_4i_rv32gc rv32gc div_4_4_rv32gc
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IDIV_ON_FPU 1
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deriv div_2_1_rv64gc rv64gc
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RADIX 32'd2
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DIVCOPIES 32'd1
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deriv div_2_2_rv64gc rv64gc
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RADIX 32'd2
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DIVCOPIES 32'd2
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deriv div_2_4_rv64gc rv64gc
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RADIX 32'd2
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DIVCOPIES 32'd4
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deriv div_4_1_rv64gc rv64gc
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RADIX 32'd4
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DIVCOPIES 32'd1
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deriv div_4_2_rv64gc rv64gc
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RADIX 32'd4
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DIVCOPIES 32'd2
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deriv div_4_4_rv64gc rv64gc
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RADIX 32'd4
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DIVCOPIES 32'd4
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deriv div_2_1i_rv64gc rv64gc div_2_1_rv64gc
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IDIV_ON_FPU 1
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deriv div_2_2i_rv64gc rv64gc div_2_2_rv64gc
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IDIV_ON_FPU 1
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deriv div_2_4i_rv64gc rv64gc div_2_4_rv64gc
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IDIV_ON_FPU 1
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deriv div_4_1i_rv64gc rv64gc div_4_1_rv64gc
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IDIV_ON_FPU 1
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deriv div_4_2i_rv64gc rv64gc div_4_2_rv64gc
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IDIV_ON_FPU 1
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deriv div_4_4i_rv64gc rv64gc div_4_4_rv64gc
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IDIV_ON_FPU 1
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# RAM latency and Burst mode for bus stress testing
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deriv ram_0_0_rv64gc rv64gc
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RAM_LATENCY 0
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BURST_EN 0
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deriv ram_1_0_rv64gc rv64gc
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RAM_LATENCY 1
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BURST_EN 0
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deriv ram_2_0_rv64gc rv64gc
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RAM_LATENCY 2
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BURST_EN 0
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deriv ram_1_1_rv64gc rv64gc
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RAM_LATENCY 1
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BURST_EN 1
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deriv ram_2_1_rv64gc rv64gc
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RAM_LATENCY 2
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BURST_EN 1
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# Branch predictor simulations
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deriv bpred_GSHARE_6_16_10_1_rv32gc rv32gc
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BPRED_SIZE 6
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deriv bpred_GSHARE_8_16_10_1_rv32gc rv32gc
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BPRED_SIZE 8
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deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc
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BPRED_SIZE 10
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deriv bpred_GSHARE_12_16_10_1_rv32gc rv32gc
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BPRED_SIZE 12
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deriv bpred_GSHARE_14_16_10_1_rv32gc rv32gc
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BPRED_SIZE 14
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deriv bpred_GSHARE_16_16_10_1_rv32gc rv32gc
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BPRED_SIZE 16
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deriv bpred_TWOBIT_6_16_10_1_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc
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BPRED_TYPE BP_TWOBIT
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deriv bpred_TWOBIT_8_16_10_1_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc
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BPRED_TYPE BP_TWOBIT
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deriv bpred_TWOBIT_10_16_10_1_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc
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BPRED_TYPE BP_TWOBIT
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deriv bpred_TWOBIT_12_16_10_1_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc
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BPRED_TYPE BP_TWOBIT
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deriv bpred_TWOBIT_14_16_10_1_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc
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BPRED_TYPE BP_TWOBIT
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deriv bpred_TWOBIT_16_16_10_1_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc
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BPRED_TYPE BP_TWOBIT
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deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc
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RAS_SIZE 2
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deriv bpred_GSHARE_10_3_10_1_rv32gc rv32gc
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RAS_SIZE 3
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deriv bpred_GSHARE_10_4_10_1_rv32gc rv32gc
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RAS_SIZE 4
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deriv bpred_GSHARE_10_6_10_1_rv32gc rv32gc
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RAS_SIZE 6
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deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc
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RAS_SIZE 10
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deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc
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RAS_SIZE 16
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deriv bpred_GSHARE_10_2_6_1_rv32gc rv32gc
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BTB_SIZE 6
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deriv bpred_GSHARE_10_2_8_1_rv32gc rv32gc
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BTB_SIZE 8
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deriv bpred_GSHARE_10_2_12_1_rv32gc rv32gc
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BTB_SIZE 12
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deriv bpred_GSHARE_10_2_14_1_rv32gc rv32gc
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BTB_SIZE 14
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deriv bpred_GSHARE_10_2_16_1_rv32gc rv32gc
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BTB_SIZE 16
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deriv bpred_GSHARE_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc
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ICLASSPRED 0
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deriv bpred_GSHARE_8_16_10_0_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc
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ICLASSPRED 0
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deriv bpred_GSHARE_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc
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ICLASSPRED 0
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deriv bpred_GSHARE_12_16_10_0_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc
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ICLASSPRED 0
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deriv bpred_GSHARE_14_16_10_0_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc
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ICLASSPRED 0
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deriv bpred_GSHARE_16_16_10_0_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc
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ICLASSPRED 0
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deriv bpred_TWOBIT_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_0_rv32gc
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ICLASSPRED 0
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deriv bpred_TWOBIT_8_16_10_0_rv32gc rv32gc bpred_GSHARE_8_16_10_0_rv32gc
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ICLASSPRED 0
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deriv bpred_TWOBIT_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_0_rv32gc
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ICLASSPRED 0
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deriv bpred_TWOBIT_12_16_10_0_rv32gc rv32gc bpred_GSHARE_12_16_10_0_rv32gc
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ICLASSPRED 0
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deriv bpred_TWOBIT_14_16_10_0_rv32gc rv32gc bpred_GSHARE_14_16_10_0_rv32gc
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ICLASSPRED 0
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deriv bpred_TWOBIT_16_16_10_0_rv32gc rv32gc bpred_GSHARE_16_16_10_0_rv32gc
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ICLASSPRED 0
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deriv bpred_GSHARE_10_2_10_0_rv32gc rv32gc bpred_GSHARE_10_2_10_1_rv32gc
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ICLASSPRED 0
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deriv bpred_GSHARE_10_3_10_0_rv32gc rv32gc bpred_GSHARE_10_3_10_1_rv32gc
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ICLASSPRED 0
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deriv bpred_GSHARE_10_4_10_0_rv32gc rv32gc bpred_GSHARE_10_4_10_1_rv32gc
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ICLASSPRED 0
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deriv bpred_GSHARE_10_6_10_0_rv32gc rv32gc bpred_GSHARE_10_6_10_1_rv32gc
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ICLASSPRED 0
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deriv bpred_GSHARE_10_2_10_0_rv32gc rv32gc bpred_GSHARE_10_2_10_1_rv32gc
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ICLASSPRED 0
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deriv bpred_GSHARE_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc
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ICLASSPRED 0
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deriv bpred_GSHARE_10_2_6_0_rv32gc rv32gc bpred_GSHARE_10_2_6_1_rv32gc
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ICLASSPRED 0
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deriv bpred_GSHARE_10_2_8_0_rv32gc rv32gc bpred_GSHARE_10_2_8_1_rv32gc
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ICLASSPRED 0
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deriv bpred_GSHARE_10_2_12_0_rv32gc rv32gc bpred_GSHARE_10_2_12_1_rv32gc
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ICLASSPRED 0
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deriv bpred_GSHARE_10_2_14_0_rv32gc rv32gc bpred_GSHARE_10_2_14_1_rv32gc
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ICLASSPRED 0
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deriv bpred_GSHARE_10_2_16_0_rv32gc rv32gc bpred_GSHARE_10_2_16_1_rv32gc
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ICLASSPRED 0
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# Cache configurations
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deriv noicache_rv32gc rv32gc
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ICACHE_SUPPORTED 0
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deriv nodcache_rv32gc rv32gc
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DCACHE_SUPPORTED 0
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deriv nocache_rv32gc rv32gc
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ICACHE_SUPPORTED 0
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DCACHE_SUPPORTED 0
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deriv way_1_4096_512_rv32gc rv32gc
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DCACHE_NUMWAYS 1
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DCACHE_WAYSIZEINBYTES 4096
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DCACHE_LINELENINBITS 512
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ICACHE_NUMWAYS 1
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ICACHE_WAYSIZEINBYTES 4096
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ICACHE_LINELENINBITS 512
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deriv way_2_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc
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DCACHE_NUMWAYS 1
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ICACHE_NUMWAYS 1
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deriv way_4_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc
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DCACHE_NUMWAYS 4
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ICACHE_NUMWAYS 4
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deriv way_4_2048_512_rv32gc rv32gc way_4_4096_512_rv32gc
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DCACHE_WAYSIZEINBYTES 2048
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ICACHE_WAYSIZEINBYTES 2048
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deriv way_4_4096_256_rv32gc rv32gc way_4_4096_512_rv32gc
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DCACHE_LINELENINBITS 256
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ICACHE_LINELENINBITS 256
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deriv way_4_4096_1024_rv32gc rv32gc way_4_4096_512_rv32gc
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DCACHE_LINELENINBITS 1024
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ICACHE_LINELENINBITS 1024
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deriv noicache_rv64gc rv64gc
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ICACHE_SUPPORTED 0
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deriv nodcache_rv64gc rv64gc
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DCACHE_SUPPORTED 0
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deriv nocache_rv64gc rv64gc
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ICACHE_SUPPORTED 0
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DCACHE_SUPPORTED 0
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deriv way_1_4096_512_rv64gc rv64gc
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DCACHE_NUMWAYS 1
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DCACHE_WAYSIZEINBYTES 4096
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DCACHE_LINELENINBITS 512
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ICACHE_NUMWAYS 1
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ICACHE_WAYSIZEINBYTES 4096
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ICACHE_LINELENINBITS 512
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|
||||
deriv way_2_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc
|
||||
DCACHE_NUMWAYS 1
|
||||
ICACHE_NUMWAYS 1
|
||||
|
||||
deriv way_4_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc
|
||||
DCACHE_NUMWAYS 4
|
||||
ICACHE_NUMWAYS 4
|
||||
|
||||
deriv way_4_2048_512_rv64gc rv64gc way_4_4096_512_rv64gc
|
||||
DCACHE_WAYSIZEINBYTES 2048
|
||||
ICACHE_WAYSIZEINBYTES 2048
|
||||
|
||||
deriv way_4_4096_256_rv64gc rv64gc way_4_4096_512_rv64gc
|
||||
DCACHE_LINELENINBITS 256
|
||||
ICACHE_LINELENINBITS 256
|
||||
|
||||
deriv way_4_4096_1024_rv64gc rv64gc way_4_4096_512_rv64gc
|
||||
DCACHE_LINELENINBITS 1024
|
||||
ICACHE_LINELENINBITS 1024
|
||||
|
||||
# TLB Size variants
|
||||
|
||||
deriv tlb2_rv32gc rv32gc
|
||||
ITLB_ENTRIES 2
|
||||
DTLB_ENTRIES 2
|
||||
|
||||
deriv tlb16_rv32gc rv32gc
|
||||
ITLB_ENTRIES 16
|
||||
DTLB_ENTRIES 16
|
||||
|
||||
deriv tlb2_rv64gc rv64gc
|
||||
ITLB_ENTRIES 2
|
||||
DTLB_ENTRIES 2
|
||||
|
||||
deriv tlb16_rv64gc rv64gc
|
||||
ITLB_ENTRIES 16
|
||||
DTLB_ENTRIES 16
|
||||
|
||||
# Feature variants
|
||||
|
||||
deriv misaligned_rv32gc rv32gc
|
||||
ZICCLSM_SUPPORTED 1
|
||||
|
||||
deriv nomisaligned_rv64gc rv64gc
|
||||
ZICCLSM_SUPPORTED 0
|
||||
|
||||
deriv nobigendian_rv32gc rv32gc
|
||||
BIGENDIAN_SUPPORTED 0
|
||||
|
||||
deriv nobigendian_rv64gc rv64gc
|
||||
BIGENDIAN_SUPPORTED 0
|
||||
|
||||
# Floating-point modes supported
|
||||
|
||||
deriv f_rv32gc rv32gc
|
||||
MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
||||
ZFH_SUPPORTED 0
|
||||
|
||||
deriv fh_rv32gc rv32gc
|
||||
MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
||||
ZFH_SUPPORTED 1
|
||||
|
||||
deriv fdh_rv32gc rv32gc
|
||||
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
||||
ZFH_SUPPORTED 1
|
||||
|
||||
deriv fdq_rv32gc rv32gc
|
||||
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
||||
ZFH_SUPPORTED 0
|
||||
|
||||
deriv fdqh_rv32gc rv32gc
|
||||
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
||||
ZFH_SUPPORTED 1
|
||||
|
||||
deriv f_rv64gc rv64gc
|
||||
MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
||||
ZFH_SUPPORTED 0
|
||||
|
||||
deriv fh_rv64gc rv64gc
|
||||
MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
||||
ZFH_SUPPORTED 1
|
||||
|
||||
deriv fd_rv64gc rv64gc
|
||||
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
||||
ZFH_SUPPORTED 0
|
||||
|
||||
deriv fdq_rv64gc rv64gc
|
||||
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
||||
ZFH_SUPPORTED 0
|
||||
|
||||
deriv fdqh_rv64gc rv64gc
|
||||
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
||||
ZFH_SUPPORTED 1
|
||||
|
||||
@ -132,6 +132,10 @@ localparam AHBW = 32'd32;
|
||||
|
||||
// Test modes
|
||||
|
||||
// AHB
|
||||
localparam RAM_LATENCY = 0;
|
||||
localparam BURST_EN = 1;
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
localparam GPIO_LOOPBACK_TEST = 1;
|
||||
localparam SPI_LOOPBACK_TEST = 0;
|
||||
@ -154,6 +158,7 @@ localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
localparam ICLASSPRED = 0;
|
||||
|
||||
localparam SVADU_SUPPORTED = 0;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
@ -133,6 +133,10 @@ localparam AHBW = 32'd32;
|
||||
|
||||
// Test modes
|
||||
|
||||
// AHB
|
||||
localparam RAM_LATENCY = 0;
|
||||
localparam BURST_EN = 1;
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
localparam GPIO_LOOPBACK_TEST = 1;
|
||||
localparam SPI_LOOPBACK_TEST = 1;
|
||||
@ -166,6 +170,7 @@ localparam RAS_SIZE = `RAS_SIZE;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
`endif
|
||||
localparam ICLASSPRED = 1;
|
||||
|
||||
localparam SVADU_SUPPORTED = 1;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
@ -132,6 +132,10 @@ localparam AHBW = 32'd32;
|
||||
|
||||
// Test modes
|
||||
|
||||
// AHB
|
||||
localparam RAM_LATENCY = 0;
|
||||
localparam BURST_EN = 1;
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
localparam GPIO_LOOPBACK_TEST = 1;
|
||||
localparam SPI_LOOPBACK_TEST = 1;
|
||||
@ -155,6 +159,7 @@ localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
localparam ICLASSPRED = 0;
|
||||
|
||||
localparam SVADU_SUPPORTED = 0;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
@ -131,6 +131,10 @@ localparam AHBW = 32'd32;
|
||||
|
||||
// Test modes
|
||||
|
||||
// AHB
|
||||
localparam RAM_LATENCY = 0;
|
||||
localparam BURST_EN = 1;
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
localparam GPIO_LOOPBACK_TEST = 1;
|
||||
localparam SPI_LOOPBACK_TEST = 1;
|
||||
@ -153,6 +157,7 @@ localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
localparam ICLASSPRED = 0;
|
||||
|
||||
localparam SVADU_SUPPORTED = 0;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
@ -134,6 +134,10 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
|
||||
|
||||
// Test modes
|
||||
|
||||
// AHB
|
||||
localparam RAM_LATENCY = 0;
|
||||
localparam BURST_EN = 1;
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
localparam GPIO_LOOPBACK_TEST = 1;
|
||||
localparam SPI_LOOPBACK_TEST = 1;
|
||||
@ -156,6 +160,7 @@ localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
localparam ICLASSPRED = 1;
|
||||
|
||||
localparam SVADU_SUPPORTED = 0;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
@ -134,6 +134,10 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
|
||||
|
||||
// Test modes
|
||||
|
||||
// AHB
|
||||
localparam RAM_LATENCY = 0;
|
||||
localparam BURST_EN = 1;
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
localparam GPIO_LOOPBACK_TEST = 1;
|
||||
localparam SPI_LOOPBACK_TEST = 1;
|
||||
@ -156,6 +160,7 @@ localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
localparam ICLASSPRED = 1;
|
||||
|
||||
localparam SVADU_SUPPORTED = 1;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
@ -180,3 +185,4 @@ localparam ZCD_SUPPORTED = 0;
|
||||
localparam USE_SRAM = 0;
|
||||
|
||||
`include "config-shared.vh"
|
||||
|
||||
|
||||
@ -134,6 +134,10 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
|
||||
|
||||
// Test modes
|
||||
|
||||
// AHB
|
||||
localparam RAM_LATENCY = 0;
|
||||
localparam BURST_EN = 1;
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
localparam GPIO_LOOPBACK_TEST = 1;
|
||||
localparam SPI_LOOPBACK_TEST = 1;
|
||||
@ -156,6 +160,7 @@ localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
localparam ICLASSPRED = 0;
|
||||
|
||||
localparam SVADU_SUPPORTED = 0;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
all: riscoftests memfiles coveragetests
|
||||
all: riscoftests memfiles coveragetests deriv
|
||||
# *** Build old tests/imperas-riscv-tests for now;
|
||||
# Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test
|
||||
# DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired
|
||||
@ -60,3 +60,7 @@ memfiles:
|
||||
|
||||
coveragetests:
|
||||
make -C ../tests/coverage/ --jobs
|
||||
|
||||
deriv:
|
||||
derivgen.pl
|
||||
|
||||
@ -5,10 +5,10 @@ export PATH=$PATH:/usr/local/bin/
|
||||
verilator=`which verilator`
|
||||
|
||||
basepath=$(dirname $0)/..
|
||||
for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do
|
||||
for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc; do
|
||||
#for config in rv64gc; do
|
||||
echo "$config linting..."
|
||||
if !($verilator --no-timing --lint-only "$@" --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
|
||||
if !($verilator --no-timing --lint-only "$@" --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
|
||||
echo "Exiting after $config lint due to errors or warnings"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
Loading…
Reference in New Issue
Block a user