Github_Repos/cvw
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7,124 Commits 5 Branches 2 Tags 53 MiB
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832 Commits

Author SHA1 Message Date
Harshini Srinath
69711503a8
Fixed formatting 2023-07-30 17:39:37 -07:00
Harshini Srinath
70599d3153
Fixed formatting 2023-07-30 17:38:22 -07:00
Harshini Srinath
2846a2f567
Fixed spacing 2023-07-30 17:32:46 -07:00
Harshini Srinath
fffde4ef7d
Fixed spacing 2023-07-30 17:22:40 -07:00
Harshini Srinath
31c09cf3cf
Fixed spacing 2023-07-30 17:21:52 -07:00
Harshini Srinath
c49944a495
Fixed spacing 2023-07-30 17:21:22 -07:00
Harshini Srinath
84d72bc203
Fixed spacing 2023-07-30 17:18:25 -07:00
Harshini Srinath
b8570c4bef
Fixed spacing 2023-07-30 16:59:27 -07:00
Harshini Srinath
872f9ed9cc
Fixed spacing 2023-07-30 16:57:57 -07:00
David Harris
f7f4c5fa7b renamed test-shared.vh to config-shared.vh 2023-07-30 05:22:39 -07:00
David Harris
388d699baa Cleaned up lint for plic_apb part select 2023-07-30 02:00:38 -07:00
David Harris
54d6a1afa2 Fixed Questa warnings in plic_apb about part select out of bounds 2023-07-30 01:54:41 -07:00
Ross Thompson
8d88ef93bc Fixed a very subtle combinational loop bug the SSTC implementation of csrs.sv. STIMCMPH did not assign all XLEN bits of CSRSReadValM so dc_shell produced d-latches and vivado created a combinational loop. 2023-07-28 11:20:29 -05:00
Ross Thompson
52dc71507f Fixed lint errors for issue #368. Does not fix simulation errors. We made a design decision a long time ago to not support DTIM on the rv32gc config because LLEN was greater than XLEN. 2023-07-26 15:08:01 -05:00
Ross Thompson
1b8edacd8d Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-25 15:13:07 -05:00
David Harris
0cfb5c7b3a Formatting cleanup 2023-07-25 05:11:38 -07:00
Ross Thompson
717833b11a Removed all old references to the old flash card controller. 
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
 2023-07-24 15:45:57 -05:00
Ross Thompson
6099b0e763 Fixed bugs in boot and new flash card merge. Works with arty a7 now. 2023-07-22 15:52:25 -05:00
Ross Thompson
3eeecd2f27 Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Ross Thompson
0063665baf Improved the critical path even more. The Arty A7 works upto 19Mhz easily. Testing out 22Mhz now. 2023-07-21 16:31:26 -05:00
Ross Thompson
37078f3d9b Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card. 2023-07-21 13:06:27 -05:00
Jacob Pease
36785848a5 Working new boot process. Buildroot package for sdc. 2023-07-20 14:15:59 -05:00
Ross Thompson
9ba3113e9c Improved critical path. 2023-07-19 14:59:37 -05:00
Ross Thompson
936b2a8c8b Optimized critial path in ifu's spill logic. 2023-07-19 14:13:46 -05:00
Ross Thompson
0e22fe5231 Removed QEMU from configurations. 2023-07-19 10:23:55 -05:00
Ross Thompson
3bf2b35704 Wow. The newest version of Vivado does not like the enums as parameters. 
The solution is simple.  I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
 2023-07-18 15:07:10 -05:00
Ross Thompson
c7283f8c83 Merge branch 'main' of github.com:ross144/cvw 2023-07-17 15:52:27 -05:00
Ross Thompson
80093a0eb1 Updated the FPGA zero stage bootloader. 2023-07-17 15:52:13 -05:00
Ross Thompson
20751790f6 Fixed bug with performance counters not tracking the correct number of requested icache and dcache memory operations. 2023-07-14 16:31:44 -05:00
Jacob Pease
142ec857ed Modified bootloader to access GUID partitions. SDC interrupt to PLIC. 
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.

The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself  was modified to accept the
SDC interrupt signal.
 2023-07-14 13:36:44 -05:00
David Harris
45667c9f4d Clean up privilege rs1 decoding and implement svinval as sfence.vma 2023-07-13 02:41:17 -07:00
Ross Thompson
58dfc15844 Merge branch 'main' of github.com:ross144/cvw into main 2023-07-11 15:08:26 -05:00
Ross Thompson
c12bc4f435 Created separate temporary testbench for xcelium. 2023-07-11 15:07:33 -05:00
Ross Thompson
05b1cce2d1 RTL changes for Xcelium. 2023-07-11 10:51:02 -05:00
Ross Thompson
e647937b27 Fixed the privilege decoder bug which prevented the fpga linux boot. 2023-07-10 17:00:06 -05:00
Ross Thompson
47ee92d6e5
Merge pull request #359 from davidharrishmc/dev 
CSR updates
 2023-07-10 13:16:57 -04:00
David Harris
c91bbc3ca8 MENVCFG only exists if U_SUPPORTED 2023-07-09 18:25:07 -07:00
Ross Thompson
4e54e5169b Changes for xcelium. 2023-07-07 18:22:28 -05:00
Ross Thompson
40b2f7ff9c Updated comments. 2023-07-06 15:24:26 -05:00
Ross Thompson
dc50ddd75e Removed unused parameter. 2023-07-06 14:57:07 -05:00
Ross Thompson
0394f3232f Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-06 14:55:43 -05:00
David Harris
74a573cedd Removed outdated commment about endianness 2023-07-06 12:41:46 -07:00
David Harris
29e62f05a4 Removed MTINST, which is not used in a system without a hypervisor 2023-07-06 12:40:53 -07:00
Ross Thompson
18278b7f4d It's a bit hacky, but the plic now passes the regression test and should be compatible with the fpga. 2023-07-06 14:07:37 -05:00
Ross Thompson
ba9d5287d9 This is at least functionally correct, but has verilator lint issues. 2023-07-06 11:53:34 -05:00
Ross Thompson
930aed0898 closer, but the wally32/64priv tests are failing. 2023-07-05 17:47:38 -05:00
Ross Thompson
c0fdd3fbca Partially solved fpga boot. 2023-07-05 17:30:55 -05:00
David Harris
19efc4eda8 Fixed comment typo 2023-07-04 11:34:58 -07:00
David Harris
4f07d89d74 fixed spacing in fdivsqrt 2023-07-04 11:27:36 -07:00
David Harris
e6ba362794 Added prefetch instructions; sent cbo instructions to LSU 2023-07-02 10:55:35 -07:00
David Harris
cc87317189 Added prefetch signals 2023-07-02 10:06:58 -07:00
David Harris
a5c6ae1f78 Enhanced decoder to produce individual CMOpE output for the 4 CMO instructions 2023-07-02 09:35:05 -07:00
David Harris
6a88ac28e4 Fixed csr typos 2023-07-02 02:01:40 -07:00
David Harris
96477a4879 Fixed ENVCFG to reply on both MENVCFG and SENVCFG when in user mode 2023-07-02 02:00:27 -07:00
David Harris
e2708534cd Added environment configuration control (menvcfg/senvcfg) of cbo instructions 2023-07-02 01:52:25 -07:00
David Harris
4d1ddd0c91 Gated floating-point load/stores with STATUS_FS and added initial decoding for Cache Management Operations 2023-07-02 00:34:30 -07:00
David Harris
110dd42cfb improved decoder checking atomic and RW and MW and privileged instructions 2023-07-02 00:02:03 -07:00
David Harris
07cf1dd9da improved decoder checking atomic instructions 2023-07-01 23:10:57 -07:00
David Harris
e05288afd9 Improved instruction decoding for illegal floating-point loads/stores and fences 2023-07-01 22:48:04 -07:00
Ross Thompson
1d2eb60ffb Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-18 16:37:19 -05:00
David Harris
95960620a2 Removed redundant and not-covered atomic check from StoreStallD 2023-06-16 16:05:53 -07:00
Ross Thompson
2f35bec970 FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization. 2023-06-16 15:40:13 -05:00
Ross Thompson
6d31936e89 Added comment to uart LCR to check reset value after updating FPGA. 2023-06-15 15:39:51 -05:00
Ross Thompson
34d1d50b87 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 15:38:38 -05:00
Ross Thompson
a011b7d591 Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
a55bcad5c1 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 14:57:23 -05:00
David Harris
52ab586a9d Added input gating on FPU 2023-06-15 12:38:33 -07:00
David Harris
524d8e8469 Gated MDU to save power; doesn't seem to have affected simulation time 2023-06-15 12:17:23 -07:00
David Harris
c7d06382b3 Bit manipulation comment cleanup 2023-06-15 12:16:46 -07:00
Ross Thompson
44c72c20e2 Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems. 2023-06-15 14:05:44 -05:00
David Harris
33ff9766b4 Gated inputs to BMU when inactive to save power and simulation time 2023-06-15 11:56:59 -07:00
Ross Thompson
2fc8080102 Got the srams parameterized correctly now. 2023-06-15 13:42:24 -05:00
David Harris
e0b6a2d693 Fixed UART merge conflict 2023-06-15 11:36:37 -07:00
Ross Thompson
e431f90cf3 Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
Harshini Srinath
37c930bb27
Update wallypipelinedsoc.sv 
Program clean up
 2023-06-15 10:39:37 -07:00
Harshini Srinath
fd00067b7f
Update wallypipelinedcore.sv 
Program clean up
 2023-06-15 10:38:38 -07:00
Harshini Srinath
e3f8280ff9
Update cvw.sv 
Program clean up
 2023-06-15 10:29:33 -07:00
Harshini Srinath
e9cfbd95f4
Update uncore.sv 
Program clean up
 2023-06-15 10:23:47 -07:00
Harshini Srinath
5d8e120031
Update uart_apb.sv 
Program clean up
 2023-06-15 10:21:46 -07:00
Harshini Srinath
53ad51ae54
Update uartPC16550D.sv 
Program clean up
 2023-06-15 10:20:29 -07:00
Harshini Srinath
ae165b35f9
Update rom_ahb.sv 
Program clean up
 2023-06-15 10:13:15 -07:00
Harshini Srinath
97917c2a44
Update ram_ahb.sv 
Program clean up
 2023-06-15 10:10:38 -07:00
Harshini Srinath
a9495e8595
Update plic_apb.sv 
Program clean up
 2023-06-15 10:08:16 -07:00
Harshini Srinath
afa0bcdd16
Update gpio_apb.sv 
Program clean up
 2023-06-15 10:04:28 -07:00
Harshini Srinath
83acb77507
Update clint_apb.sv 
Program clean up
 2023-06-15 09:59:11 -07:00
David Harris
380c9e1dde Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-06-15 07:01:44 -07:00
Ross Thompson
6bb5f32eb9 Improved simulation speed by gating bitmanip zbc's clmul's X and Y inputs with BSelect != 11. Reduced simulation time from 3m45s to 2m35s. 2023-06-14 15:28:58 -05:00
Harshini Srinath
e0a30ecc22
Merge branch 'main' into main 2023-06-14 11:52:45 -07:00
David Harris
fe35f9ecdb Moved cvw.sv to src root directory to avoid double-compiling and producing a warning. Adjusted to files to reflect this. 2023-06-14 09:44:52 -07:00
David Harris
59bf356064 Removed *** from UART code 2023-06-14 08:47:01 -07:00
David Harris
ea805d32ec Removed QEMU from UART 2023-06-14 08:39:01 -07:00
Harshini Srinath
629ccb191f
Update csrs.sv 
Program clean up
 2023-06-13 22:16:43 -07:00
Harshini Srinath
49c84f888f
Update csrm.sv 
Program clean up
 2023-06-13 22:08:06 -07:00
Harshini Srinath
aff15a0a46
Update csrc.sv 
Program clean up
 2023-06-13 21:54:47 -07:00
Harshini Srinath
fb019a736c
Update csr.sv 
Program clean up
 2023-06-13 21:12:49 -07:00
harshini
17724f7832 deleting CodeAligner file 2023-06-13 17:41:37 -07:00
Harshini Srinath
58c617c548
Update ahbapbbridge.sv 
Program clean up
 2023-06-12 20:49:46 -07:00
Harshini Srinath
475e11e03f
Update trap.sv 
Program clean up
 2023-06-12 20:31:44 -07:00
Harshini Srinath
e2af1fabd2
Update privmode.sv 
Program clean up
 2023-06-12 20:27:48 -07:00
Harshini Srinath
ac7043770d
Update privileged.sv 
Program clean up
 2023-06-12 20:26:07 -07:00