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Fixed bugs in boot and new flash card merge. Works with arty a7 now.

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This commit is contained in:
Ross Thompson 2023-07-22 15:33:33 -05:00
parent 608400ac6a
commit 6099b0e763
3 changed files with 14 additions and 5 deletions
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2
config/fpga/config.vh
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@ -107,7 +107,7 @@ localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
localparam UNCORE_RAM_SUPPORTED = 1'b1;
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80002000;
localparam logic [63:0] UNCORE_RAM_BASE = 64'h00002000;
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h00000FFF;
localparam EXT_MEM_SUPPORTED = 1'b1;

12
fpga/src/fpgaTopArtyA7.v
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@ -135,7 +135,7 @@ module fpgaTop
wire [2:0] BUS_axi_awsize;
wire [1:0] BUS_axi_awburst;
wire [3:0] BUS_axi_awcache;
wire [30:0] BUS_axi_awaddr;
wire [31:0] BUS_axi_awaddr;
wire [2:0] BUS_axi_awprot;
wire BUS_axi_awvalid;
wire BUS_axi_awready;
@ -156,7 +156,7 @@ module fpgaTop
wire [2:0] BUS_axi_arprot;
wire [3:0] BUS_axi_arcache;
wire BUS_axi_arvalid;
wire [30:0] BUS_axi_araddr;
wire [31:0] BUS_axi_araddr;
wire BUS_axi_arlock;
wire BUS_axi_arready;
wire [3:0] BUS_axi_rid;
@ -167,7 +167,8 @@ module fpgaTop
wire BUS_axi_rready;
wire BUSCLK;
wire sdio_reset_open;
// Crossbar to Bus ------------------------------------------------
(* mark_debug = "true" *)wire s00_axi_aclk;
@ -192,6 +193,7 @@ module fpgaTop
(* mark_debug = "true" *)wire [1:0]s00_axi_bresp;
(* mark_debug = "true" *)wire s00_axi_bvalid;
(* mark_debug = "true" *)wire s00_axi_bready;
wire [3:0] s00_axi_arid;
(* mark_debug = "true" *)wire [31:0]s00_axi_araddr;
(* mark_debug = "true" *)wire [7:0]s00_axi_arlen;
(* mark_debug = "true" *)wire [2:0]s00_axi_arsize;
@ -237,6 +239,7 @@ module fpgaTop
wire s01_axi_bready;
wire [31:0]s01_axi_araddr;
wire [7:0]s01_axi_arlen;
wire [3:0] s01_axi_arid;
wire [2:0]s01_axi_arsize;
wire [1:0]s01_axi_arburst;
wire [0:0]s01_axi_arlock;
@ -525,7 +528,7 @@ module fpgaTop
xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0
(.s_ahb_hclk(CPUCLK),
.s_ahb_hresetn(peripheral_aresetn),
.s_ahb_hsel(HSELEXT),
.s_ahb_hsel(HSELEXT | HSELEXTSDC),
.s_ahb_haddr(HADDR[31:0]),
.s_ahb_hprot(HPROT),
.s_ahb_htrans(HTRANS),
@ -833,6 +836,7 @@ module fpgaTop
.s_axi_rresp(SDCin_axi_rresp),
.s_axi_rvalid(SDCin_axi_rvalid),
.s_axi_rready(SDCin_axi_rready),
.sdio_reset(sdio_reset_open),
// Master Interface
.m_axi_awaddr(SDCout_axi_awaddr),

5
src/uncore/uncore.sv
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@ -146,6 +146,11 @@ module uncore import cvw::*; #(parameter cvw_t P)(
assign UARTSout = 0; assign UARTIntr = 0;
end
// eventually remove
assign HREADSDC = '0;
assign HREADYSDC = '1;
assign HRESPSDC = '0;
// AHB Read Multiplexer
assign HRDATA = ({P.XLEN{HSELRamD}} & HREADRam) |
({P.XLEN{HSELEXTD | HSELEXTSDCD}} & HRDATAEXT) |