Ross Thompson 2fc8080102 Got the srams parameterized correctly now.		2023-06-15 13:42:24 -05:00
..
cache	Got the srams parameterized correctly now.	2023-06-15 13:42:24 -05:00
ebu	More parameterization. Based on Lim's work. EBU, IFU (except bpred), and IEU done.	2023-05-24 14:56:02 -05:00
fpu	Update some spacing to make it look better	2023-06-05 11:03:06 -05:00
generic	Got the srams parameterized correctly now.	2023-06-15 13:42:24 -05:00
hazard	MDU and hazard unit now also parameterized. Based on Lim's work. Again I want to clarify this their work. Not mine. I'm just doing this because the merge had an issue.	2023-05-24 15:01:35 -05:00
ieu	Found a whole bunch of files still using the old `define configurations.	2023-06-15 13:09:07 -05:00
ifu	Got the srams parameterized correctly now.	2023-06-15 13:42:24 -05:00
lsu	Got the srams parameterized correctly now.	2023-06-15 13:42:24 -05:00
mdu	Found a whole bunch of files still using the old `define configurations.	2023-06-15 13:09:07 -05:00
mmu	Found a whole bunch of files still using the old `define configurations.	2023-06-15 13:09:07 -05:00
privileged	Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem.	2023-06-05 15:42:05 -05:00
uncore	Got the srams parameterized correctly now.	2023-06-15 13:42:24 -05:00
wally	This parameterizes the testbench but does not use the verilator updates or the new testbench.	2023-06-12 11:00:30 -05:00