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fixed spacing in fdivsqrt

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This commit is contained in:
David Harris 2023-07-04 11:27:36 -07:00
parent 4c921fc797
commit 4f07d89d74
9 changed files with 75 additions and 76 deletions
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44
src/fpu/fdivsqrt/fdivsqrt.sv
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@ -27,24 +27,24 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module fdivsqrt import cvw::*; #(parameter cvw_t P) (
input logic clk,
input logic reset,
input logic clk,
input logic reset,
input logic [P.FMTBITS-1:0] FmtE,
input logic XsE,
input logic XsE,
input logic [P.NF:0] XmE, YmE,
input logic [P.NE-1:0] XeE, YeE,
input logic XInfE, YInfE,
input logic XZeroE, YZeroE,
input logic XNaNE, YNaNE,
input logic FDivStartE, IDivStartE,
input logic StallM,
input logic FlushE,
input logic SqrtE, SqrtM,
input logic XInfE, YInfE,
input logic XZeroE, YZeroE,
input logic XNaNE, YNaNE,
input logic FDivStartE, IDivStartE,
input logic StallM,
input logic FlushE,
input logic SqrtE, SqrtM,
input logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // these are the src outputs before the mux choosing between them and PCE to put in srcA/B
input logic [2:0] Funct3E, Funct3M,
input logic IntDivE, W64E,
output logic DivStickyM,
output logic FDivBusyE, IFDivStartE, FDivDoneE,
input logic [2:0] Funct3E, Funct3M,
input logic IntDivE, W64E,
output logic DivStickyM,
output logic FDivBusyE, IFDivStartE, FDivDoneE,
output logic [P.NE+1:0] QeM,
output logic [P.DIVb:0] QmM,
output logic [P.XLEN-1:0] FIntDivResultM
@ -58,19 +58,19 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) (
logic [P.DIVb+3:0] D; // Iterator Divisor
logic [P.DIVb:0] FirstU, FirstUM; // Intermediate result values
logic [P.DIVb+1:0] FirstC; // Step tracker
logic Firstun; // Quotient selection
logic WZeroE; // Early termination flag
logic Firstun; // Quotient selection
logic WZeroE; // Early termination flag
logic [P.DURLEN-1:0] CyclesE; // FSM cycles
logic SpecialCaseM; // Divide by zero, square root of negative, etc.
logic DivStartE; // Enable signal for flops during stall
logic SpecialCaseM; // Divide by zero, square root of negative, etc.
logic DivStartE; // Enable signal for flops during stall
// Integer div/rem signals
logic BZeroM; // Denominator is zero
logic IntDivM; // Integer operation
logic BZeroM; // Denominator is zero
logic IntDivM; // Integer operation
logic [P.DIVBLEN:0] nM, mM; // Shift amounts
logic NegQuotM, ALTBM, AsM, W64M; // Special handling for postprocessor
logic NegQuotM, ALTBM, AsM, W64M; // Special handling for postprocessor
logic [P.XLEN-1:0] AM; // Original Numerator for postprocessor
logic ISpecialCaseE; // Integer div/remainder special cases
logic ISpecialCaseE; // Integer div/remainder special cases
fdivsqrtpreproc #(P) fdivsqrtpreproc( // Preprocessor
.clk, .IFDivStartE, .Xm(XmE), .Ym(YmE), .Xe(XeE), .Ye(YeE),

4
src/fpu/fdivsqrt/fdivsqrtcycles.sv
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@ -28,8 +28,8 @@
module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
input logic [P.FMTBITS-1:0] FmtE,
input logic SqrtE,
input logic IntDivE,
input logic SqrtE,
input logic IntDivE,
input logic [P.DIVBLEN:0] nE,
output logic [P.DURLEN-1:0] CyclesE
);

4
src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
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@ -29,8 +29,8 @@
module fdivsqrtexpcalc import cvw::*; #(parameter cvw_t P) (
input logic [P.FMTBITS-1:0] Fmt,
input logic [P.NE-1:0] Xe, Ye,
input logic Sqrt,
input logic XZero,
input logic Sqrt,
input logic XZero,
input logic [P.DIVBLEN:0] ell, m,
output logic [P.NE+1:0] Qe
);

5
src/fpu/fdivsqrt/fdivsqrtfgen2.sv
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@ -27,18 +27,17 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module fdivsqrtfgen2 import cvw::*; #(parameter cvw_t P) (
input logic up, uz,
input logic up, uz,
input logic [P.DIVb+3:0] C, U, UM,
output logic [P.DIVb+3:0] F
);
logic [P.DIVb+3:0] FP, FN, FZ;
logic [P.DIVb+3:0] FP, FN, FZ;
// Generate for both positive and negative bits
assign FP = ~(U << 1) & C;
assign FN = (UM << 1) | (C & ~(C << 2));
assign FZ = '0;
always_comb // Choose which adder input will be used
if (up) F = FP;
else if (uz) F = FZ;

4
src/fpu/fdivsqrt/fdivsqrtfgen4.sv
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@ -27,11 +27,11 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module fdivsqrtfgen4 import cvw::*; #(parameter cvw_t P) (
input logic [3:0] udigit,
input logic [3:0] udigit,
input logic [P.DIVb+3:0] C, U, UM,
output logic [P.DIVb+3:0] F
);
logic [P.DIVb+3:0] F2, F1, F0, FN1, FN2;
logic [P.DIVb+3:0] F2, F1, F0, FN1, FN2;
// Generate for both positive and negative bits
assign F2 = (~U << 2) & (C << 2);

26
src/fpu/fdivsqrt/fdivsqrtfsm.sv
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@ -27,20 +27,20 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module fdivsqrtfsm import cvw::*; #(parameter cvw_t P) (
input logic clk, reset,
input logic XInfE, YInfE,
input logic XZeroE, YZeroE,
input logic XNaNE, YNaNE,
input logic FDivStartE, IDivStartE,
input logic XsE, WZeroE,
input logic SqrtE,
input logic StallM, FlushE,
input logic IntDivE,
input logic ISpecialCaseE,
input logic clk, reset,
input logic XInfE, YInfE,
input logic XZeroE, YZeroE,
input logic XNaNE, YNaNE,
input logic FDivStartE, IDivStartE,
input logic XsE, WZeroE,
input logic SqrtE,
input logic StallM, FlushE,
input logic IntDivE,
input logic ISpecialCaseE,
input logic [P.DURLEN-1:0] CyclesE,
output logic IFDivStartE,
output logic FDivBusyE, FDivDoneE,
output logic SpecialCaseM
output logic IFDivStartE,
output logic FDivBusyE, FDivDoneE,
output logic SpecialCaseM
);
typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype;

16
src/fpu/fdivsqrt/fdivsqrtiter.sv
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@ -27,14 +27,14 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module fdivsqrtiter import cvw::*; #(parameter cvw_t P) (
input logic clk,
input logic IFDivStartE,
input logic FDivBusyE,
input logic SqrtE,
input logic clk,
input logic IFDivStartE,
input logic FDivBusyE,
input logic SqrtE,
input logic [P.DIVb+3:0] X, D,
output logic [P.DIVb:0] FirstU, FirstUM,
output logic [P.DIVb+1:0] FirstC,
output logic Firstun,
output logic Firstun,
output logic [P.DIVb+3:0] FirstWS, FirstWC
);
@ -48,11 +48,11 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) (
logic [P.DIVb:0] UNext[P.DIVCOPIES-1:0]; // U1.b
logic [P.DIVb:0] UMNext[P.DIVCOPIES-1:0]; // U1.b
logic [P.DIVb+1:0] C[P.DIVCOPIES:0]; // Q2.b
logic [P.DIVb+1:0] initC; // Q2.b
logic [P.DIVb+1:0] initC; // Q2.b
logic [P.DIVCOPIES-1:0] un;
logic [P.DIVb+3:0] WSN, WCN; // Q4.b
logic [P.DIVb+3:0] DBar, D2, DBar2; // Q4.b
logic [P.DIVb+3:0] WSN, WCN; // Q4.b
logic [P.DIVb+3:0] DBar, D2, DBar2; // Q4.b
logic [P.DIVb+1:0] NextC;
logic [P.DIVb:0] UMux, UMMux;
logic [P.DIVb:0] initU, initUM;

18
src/fpu/fdivsqrt/fdivsqrtpostproc.sv
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@ -27,27 +27,27 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) (
input logic clk, reset,
input logic StallM,
input logic clk, reset,
input logic StallM,
input logic [P.DIVb+3:0] WS, WC,
input logic [P.DIVb+3:0] D,
input logic [P.DIVb:0] FirstU, FirstUM,
input logic [P.DIVb+1:0] FirstC,
input logic SqrtE,
input logic Firstun, SqrtM, SpecialCaseM, NegQuotM,
input logic SqrtE,
input logic Firstun, SqrtM, SpecialCaseM, NegQuotM,
input logic [P.XLEN-1:0] AM,
input logic RemOpM, ALTBM, BZeroM, AsM, W64M,
input logic RemOpM, ALTBM, BZeroM, AsM, W64M,
input logic [P.DIVBLEN:0] nM, mM,
output logic [P.DIVb:0] QmM,
output logic WZeroE,
output logic DivStickyM,
output logic WZeroE,
output logic DivStickyM,
output logic [P.XLEN-1:0] FIntDivResultM
);
logic [P.DIVb+3:0] W, Sum;
logic [P.DIVb:0] PreQmM;
logic NegStickyM;
logic weq0E, WZeroM;
logic NegStickyM;
logic weq0E, WZeroM;
logic [P.XLEN-1:0] IntDivResultM;
//////////////////////////

30
src/fpu/fdivsqrt/fdivsqrtpreproc.sv
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@ -27,24 +27,24 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
input logic clk,
input logic IFDivStartE,
input logic clk,
input logic IFDivStartE,
input logic [P.NF:0] Xm, Ym,
input logic [P.NE-1:0] Xe, Ye,
input logic [P.FMTBITS-1:0] FmtE,
input logic SqrtE,
input logic XZeroE,
input logic [2:0] Funct3E,
input logic SqrtE,
input logic XZeroE,
input logic [2:0] Funct3E,
output logic [P.NE+1:0] QeM,
output logic [P.DIVb+3:0] X, D,
// Int-specific
input logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
input logic IntDivE, W64E,
output logic ISpecialCaseE,
input logic IntDivE, W64E,
output logic ISpecialCaseE,
output logic [P.DURLEN-1:0] CyclesE,
output logic [P.DIVBLEN:0] nM, mM,
output logic NegQuotM, ALTBM, IntDivM, W64M,
output logic AsM, BZeroM,
output logic NegQuotM, ALTBM, IntDivM, W64M,
output logic AsM, BZeroM,
output logic [P.XLEN-1:0] AM
);
@ -54,11 +54,11 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
logic [P.NE+1:0] QeE; // Quotient Exponent (FP only)
logic [P.DIVb-1:0] IFX, IFD; // Correctly-sized inputs for iterator, selected from int or fp input
logic [P.DIVBLEN:0] mE, nE, ell; // Leading zeros of inputs
logic NumerZeroE; // Numerator is zero (X or A)
logic AZeroE, BZeroE; // A or B is Zero for integer division
logic SignedDivE; // signed division
logic NegQuotE; // Integer quotient is negative
logic AsE, BsE; // Signs of integer inputs
logic NumerZeroE; // Numerator is zero (X or A)
logic AZeroE, BZeroE; // A or B is Zero for integer division
logic SignedDivE; // signed division
logic NegQuotE; // Integer quotient is negative
logic AsE, BsE; // Signs of integer inputs
logic [P.XLEN-1:0] AE; // input A after W64 adjustment
logic ALTBE;
@ -166,7 +166,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
// Sqrt is initialized on step one as R(X-1), so depends on Radix
mux2 #(P.DIVb+1) sqrtxmux({~XZeroE, Xfract}, {1'b0, ~XZeroE, Xfract[P.DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX);
if (P.RADIX == 2) assign SqrtX = {3'b111, PreSqrtX};
if (P.RADIX == 2) assign SqrtX = {3'b111, PreSqrtX};
else assign SqrtX = {2'b11, PreSqrtX, 1'b0};
mux2 #(P.DIVb+4) prexmux(DivX, SqrtX, SqrtE, PreShiftX);