Ross Thompson
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a910425adf
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-09-14 10:16:54 -05:00 |
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Ross Thompson
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7c89154a7f
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Slight modification to cachefsm.
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2023-09-05 14:07:58 -05:00 |
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Ross Thompson
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f00df8d121
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Merge pull request #407 from davidharrishmc/dev
initial spill logic improvement
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2023-09-05 13:29:37 -05:00 |
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Ross Thompson
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e39fc44efd
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Merge pull request #406 from magpyed/cachesim_fix
Properly gate LRUWriteEn with ~FlushStage
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2023-09-05 11:10:58 -05:00 |
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David Harris
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6ab71ffca6
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initial spill logic improvement
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2023-09-03 04:21:13 -07:00 |
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David Harris
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1ced158596
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tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker
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2023-09-02 12:56:36 -07:00 |
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Limnanthes Serafini
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b334e4ff1f
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Properly gate LRUWriteEn with ~FlushStage
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2023-09-01 23:31:02 -07:00 |
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David Harris
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98fa3a78dd
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Improved tlb and controller coverage; fixed exclusions on broken lines
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2023-08-31 00:27:47 -07:00 |
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Kevin Kim
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e4ed61a2ce
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Merge branch 'openhwgroup:main' into synth_wrapper_gen
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2023-08-28 09:03:10 -07:00 |
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Kevin Kim
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fc25afb3cb
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make synth integerates wrapper generation and runs synth on wrapper
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2023-08-28 09:02:56 -07:00 |
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Ross Thompson
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e7becd53d7
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Merge pull request #398 from davidharrishmc/dev
Completed basic tests of svnapot and svpbmt
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2023-08-28 09:10:20 -05:00 |
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David Harris
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10549b7787
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Completed basic tests of svnapot and svpbmt
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2023-08-28 06:57:35 -07:00 |
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Kevin Kim
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9217e1e767
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synth works
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2023-08-26 21:11:21 -07:00 |
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David Harris
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75986d6641
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Fixed merge conflict for ZICBOP
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2023-08-25 18:41:57 -07:00 |
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David Harris
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3721f8347d
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Preparing to merge with CBO* changes
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2023-08-25 18:41:03 -07:00 |
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David Harris
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c07ad03f9d
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Initial implementation of SVNAPOT and SVPBMT does not break regression
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2023-08-25 18:33:08 -07:00 |
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David Harris
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9f44241d0f
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Added N and PBMT bits to MMU PTE
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2023-08-24 19:44:46 -07:00 |
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David Harris
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847c0dd099
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Merge pull request #393 from ross144/main
Implemented and tested CBOZ instruction
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2023-08-24 19:17:38 -07:00 |
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David Harris
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d12be1faac
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Merge pull request #394 from harshinisrinath1001/main
Improved testing of csri with priv.S!
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2023-08-24 19:16:50 -07:00 |
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harshinisrinath
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49014e61bc
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Improved testing of csri with priv.S
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2023-08-24 18:39:15 -07:00 |
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Ross Thompson
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284ff0ab0b
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Fixed minor performance bug with CBOZ.
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2023-08-24 17:08:20 -05:00 |
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Ross Thompson
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fbcf6be06d
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Now have CBOZ instructions working!
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2023-08-24 16:47:35 -05:00 |
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David Harris
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aad722ffb1
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Check for legal SATP mode values
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2023-08-24 05:18:04 -07:00 |
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Ross Thompson
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e8bc339638
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Oups there was a bug in the SATP fix. RV32GC was broken by the changes.
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2023-08-23 09:42:46 -05:00 |
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Ross Thompson
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d9a001e87a
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-08-23 09:15:13 -05:00 |
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Jacob Pease
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0f29587b0b
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Prevented writes to SATP enabling SV57. This follows the spec more accurately. Linux can now successfully probe SATP.
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2023-08-22 16:25:56 -05:00 |
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Ross Thompson
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a899be7deb
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Fixed bug with the cbo.inval clearing already cleared lines.
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2023-08-21 17:51:51 -05:00 |
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Ross Thompson
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6337aab757
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Fixed issue when with flush miss.
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2023-08-18 16:36:13 -05:00 |
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Ross Thompson
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e3bb0d2820
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Now we have invalidate, clean, and flush working.
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2023-08-18 16:32:22 -05:00 |
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Ross Thompson
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b9af790b81
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Added cbom test to custom. Needs to be moved to wally-riscv-arch-tests.
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2023-08-18 15:59:39 -05:00 |
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Ross Thompson
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b842fdb863
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Might have working cbo clean and flush instructions.
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2023-08-18 14:48:21 -05:00 |
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Ross Thompson
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8c7eafffad
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Fixed cbo instruction decode.
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2023-08-18 11:32:30 -05:00 |
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Ross Thompson
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a14966e516
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Updated the hazard logic for CMO operations.
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2023-08-17 17:58:49 -05:00 |
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Ross Thompson
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bfde4d2c78
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Found first bug in CMO implementation.
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2023-08-17 16:57:54 -05:00 |
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Ross Thompson
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6a8a82d9e8
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CMOZ now implemented in the D cache.
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2023-08-17 12:46:40 -05:00 |
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Ross Thompson
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e74e4f3a60
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Added clean and flush to cache fsm.
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2023-08-16 14:23:56 -05:00 |
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Ross Thompson
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b5ca41fd2a
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More progress towards cmo.
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2023-08-15 18:17:15 -05:00 |
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Ross Thompson
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6284773733
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The L1 D cache now supports cache line (block) invalidation and partial support for clean and flush.
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2023-08-14 16:39:18 -05:00 |
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Ross Thompson
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f678133d19
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Initial CMO implementation. Just adds control signals into the L1 caches.
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2023-08-14 15:43:12 -05:00 |
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Ross Thompson
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3e66653f37
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Cache cleanup.
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2023-07-31 14:12:53 -05:00 |
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Ross Thompson
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141e90d425
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Merge pull request #372 from davidharrishmc/dev
PLIC part select warnings fixed
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2023-07-31 11:28:28 -04:00 |
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David Harris
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55d4f28efe
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Merge pull request #373 from harshinisrinath1001/main
Improved testing of pmd in priv, fixed bugs, and attempted to reset menvcfg and fixed spacing in fpu/fma and fpu/postprocessing
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2023-07-30 22:46:44 -07:00 |
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Harshini Srinath
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01fc7c5284
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Fixed formatting
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2023-07-30 18:36:25 -07:00 |
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Harshini Srinath
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811e2fd94c
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Fixed formatting
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2023-07-30 18:30:23 -07:00 |
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Harshini Srinath
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01bbddc5da
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Fixed formatting
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2023-07-30 18:27:22 -07:00 |
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Harshini Srinath
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a697c89a2a
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Fixed formatting
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2023-07-30 18:18:24 -07:00 |
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Harshini Srinath
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1bc1a68210
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Fixed formatting
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2023-07-30 18:06:25 -07:00 |
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Harshini Srinath
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86164acc84
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Fixed formatting
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2023-07-30 18:00:39 -07:00 |
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Harshini Srinath
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6b5aa47f23
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Fixed formatting
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2023-07-30 17:54:47 -07:00 |
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Harshini Srinath
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8c7ea5a47a
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Fixed formatting
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2023-07-30 17:46:23 -07:00 |
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