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https://github.com/openhwgroup/cvw
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Update gpio_apb.sv
Program clean up
This commit is contained in:
Harshini Srinath
GitHub
parent
83acb77507
commit
afa0bcdd16
@ -29,78 +29,78 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module gpio_apb import cvw::*; #(parameter cvw_t P) (
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input logic PCLK, PRESETn,
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input logic PSEL,
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input logic [7:0] PADDR,
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input logic [P.XLEN-1:0] PWDATA,
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input logic PCLK, PRESETn,
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input logic PSEL,
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input logic [7:0] PADDR,
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input logic [P.XLEN-1:0] PWDATA,
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input logic [P.XLEN/8-1:0] PSTRB,
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input logic PWRITE,
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input logic PENABLE,
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output logic [P.XLEN-1:0] PRDATA,
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output logic PREADY,
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input logic [31:0] iof0, iof1,
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input logic [31:0] GPIOIN,
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output logic [31:0] GPIOOUT, GPIOEN,
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output logic GPIOIntr
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input logic PWRITE,
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input logic PENABLE,
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output logic [P.XLEN-1:0] PRDATA,
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output logic PREADY,
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input logic [31:0] iof0, iof1,
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input logic [31:0] GPIOIN,
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output logic [31:0] GPIOOUT, GPIOEN,
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output logic GPIOIntr
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);
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logic [31:0] input0d, input1d, input2d, input3d;
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logic [31:0] input_val, input_en, output_en, output_val;
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logic [31:0] rise_ie, rise_ip, fall_ie, fall_ip, high_ie, high_ip, low_ie, low_ip;
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logic [31:0] out_xor, iof_en, iof_sel, iof_out, gpio_out;
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logic [7:0] entry;
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logic [31:0] Din, Dout;
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logic memwrite;
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logic [31:0] input0d, input1d, input2d, input3d;
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logic [31:0] input_val, input_en, output_en, output_val;
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logic [31:0] rise_ie, rise_ip, fall_ie, fall_ip, high_ie, high_ip, low_ie, low_ip;
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logic [31:0] out_xor, iof_en, iof_sel, iof_out, gpio_out;
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logic [7:0] entry;
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logic [31:0] Din, Dout;
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logic memwrite;
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// APB I/O
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assign entry = {PADDR[7:2],2'b00}; // 32-bit word-aligned accesses
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assign entry = {PADDR[7:2],2'b00}; // 32-bit word-aligned accesses
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assign memwrite = PWRITE & PENABLE & PSEL; // only write in access phase
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assign PREADY = 1'b1; // GPIO never takes >1 cycle to respond
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assign PREADY = 1'b1; // GPIO never takes >1 cycle to respond
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// account for subword read/write circuitry
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// -- Note GPIO registers are 32 bits no matter what; access them with LW SW.
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// (At least that's what I think when FE310 spec says "only naturally aligned 32-bit accesses are supported")
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if (P.XLEN == 64) begin
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assign Din = entry[2] ? PWDATA[63:32] : PWDATA[31:0];
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assign Din = entry[2] ? PWDATA[63:32] : PWDATA[31:0];
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assign PRDATA = entry[2] ? {Dout,32'b0} : {32'b0,Dout};
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end else begin // 32-bit
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assign Din = PWDATA[31:0];
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assign Din = PWDATA[31:0];
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assign PRDATA = Dout;
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end
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// register access
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always_ff @(posedge PCLK, negedge PRESETn)
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if (~PRESETn) begin // asynch reset
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input_en <= 0;
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input_en <= 0;
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output_en <= 0;
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// *** synch reset not yet implemented [DH: can we delete this comment? Check if a sync reset is required]
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output_val <= #1 0;
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rise_ie <= #1 0;
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rise_ip <= #1 0;
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fall_ie <= #1 0;
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fall_ip <= #1 0;
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high_ie <= #1 0;
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high_ip <= #1 0;
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low_ie <= #1 0;
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low_ip <= #1 0;
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iof_en <= #1 0;
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iof_sel <= #1 0;
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out_xor <= #1 0;
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rise_ie <= #1 0;
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rise_ip <= #1 0;
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fall_ie <= #1 0;
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fall_ip <= #1 0;
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high_ie <= #1 0;
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high_ip <= #1 0;
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low_ie <= #1 0;
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low_ip <= #1 0;
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iof_en <= #1 0;
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iof_sel <= #1 0;
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out_xor <= #1 0;
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end else begin // writes
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// According to FE310 spec: Once the interrupt is pending, it will remain set until a 1 is written to the *_ip register at that bit.
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/* verilator lint_off CASEINCOMPLETE */
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if (memwrite)
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case(entry)
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8'h04: input_en <= #1 Din;
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8'h08: output_en <= #1 Din;
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8'h04: input_en <= #1 Din;
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8'h08: output_en <= #1 Din;
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8'h0C: output_val <= #1 Din;
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8'h18: rise_ie <= #1 Din;
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8'h20: fall_ie <= #1 Din;
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8'h28: high_ie <= #1 Din;
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8'h30: low_ie <= #1 Din;
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8'h38: iof_en <= #1 Din;
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8'h3C: iof_sel <= #1 Din;
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8'h40: out_xor <= #1 Din;
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8'h18: rise_ie <= #1 Din;
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8'h20: fall_ie <= #1 Din;
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8'h28: high_ie <= #1 Din;
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8'h30: low_ie <= #1 Din;
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8'h38: iof_en <= #1 Din;
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8'h3C: iof_sel <= #1 Din;
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8'h40: out_xor <= #1 Din;
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endcase
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/* verilator lint_on CASEINCOMPLETE */
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@ -115,21 +115,21 @@ module gpio_apb import cvw::*; #(parameter cvw_t P) (
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else low_ip <= low_ip | ~input3d;
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case(entry) // flop to sample inputs
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8'h00: Dout <= #1 input_val;
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8'h04: Dout <= #1 input_en;
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8'h08: Dout <= #1 output_en;
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8'h0C: Dout <= #1 output_val;
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8'h18: Dout <= #1 rise_ie;
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8'h1C: Dout <= #1 rise_ip;
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8'h20: Dout <= #1 fall_ie;
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8'h24: Dout <= #1 fall_ip;
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8'h28: Dout <= #1 high_ie;
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8'h2C: Dout <= #1 high_ip;
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8'h30: Dout <= #1 low_ie;
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8'h34: Dout <= #1 low_ip;
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8'h38: Dout <= #1 iof_en;
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8'h3C: Dout <= #1 iof_sel;
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8'h40: Dout <= #1 out_xor;
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8'h00: Dout <= #1 input_val;
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8'h04: Dout <= #1 input_en;
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8'h08: Dout <= #1 output_en;
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8'h0C: Dout <= #1 output_val;
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8'h18: Dout <= #1 rise_ie;
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8'h1C: Dout <= #1 rise_ip;
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8'h20: Dout <= #1 fall_ie;
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8'h24: Dout <= #1 fall_ip;
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8'h28: Dout <= #1 high_ie;
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8'h2C: Dout <= #1 high_ip;
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8'h30: Dout <= #1 low_ie;
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8'h34: Dout <= #1 low_ip;
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8'h38: Dout <= #1 iof_en;
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8'h3C: Dout <= #1 iof_sel;
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8'h40: Dout <= #1 out_xor;
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default: Dout <= #1 0;
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endcase
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end
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@ -137,18 +137,17 @@ module gpio_apb import cvw::*; #(parameter cvw_t P) (
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// chip i/o
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// connect OUT to IN for loopback testing
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if (P.GPIO_LOOPBACK_TEST) assign input0d = ((output_en & GPIOOUT) | (~output_en & GPIOIN)) & input_en;
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else assign input0d = GPIOIN & input_en;
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else assign input0d = GPIOIN & input_en;
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// synchroninzer for inputs
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flop #(32) sync1(PCLK,input0d,input1d);
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flop #(32) sync2(PCLK,input1d,input2d);
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flop #(32) sync3(PCLK,input2d,input3d);
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assign input_val = input3d;
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assign iof_out = iof_sel & iof1 | ~iof_sel & iof0; // per-bit mux between iof1 and iof0
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assign gpio_out = iof_en & iof_out | ~iof_en & output_val; // per-bit mux between IOF and output_val
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assign GPIOOUT = gpio_out ^ out_xor; // per-bit flip output polarity
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assign GPIOEN = output_en;
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assign iof_out = iof_sel & iof1 | ~iof_sel & iof0; // per-bit mux between iof1 and iof0
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assign gpio_out = iof_en & iof_out | ~iof_en & output_val; // per-bit mux between IOF and output_val
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assign GPIOOUT = gpio_out ^ out_xor; // per-bit flip output polarity
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assign GPIOEN = output_en;
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assign GPIOIntr = |{(rise_ip & rise_ie),(fall_ip & fall_ie),(high_ip & high_ie),(low_ip & low_ie)};
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assign GPIOIntr = |{(rise_ip & rise_ie),(fall_ip & fall_ie),(high_ip & high_ie),(low_ip & low_ie)};
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endmodule
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