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Update trap.sv
Program clean up
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@ -63,13 +63,13 @@ module trap import cvw::*; #(parameter cvw_t P) (
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assign MIntGlobalEnM = (PrivilegeModeW != P.M_MODE) | STATUS_MIE; // if M ints enabled or lower priv 3.1.9
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assign SIntGlobalEnM = (PrivilegeModeW == P.U_MODE) | ((PrivilegeModeW == P.S_MODE) & STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9
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assign PendingIntsM = MIP_REGW & MIE_REGW;
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assign IntPendingM = |PendingIntsM;
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assign Committed = CommittedM | CommittedF;
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assign EnabledIntsM = ({12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW);
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assign ValidIntsM = {12{~Committed}} & EnabledIntsM;
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assign InterruptM = (|ValidIntsM) & InstrValidM; // suppress interrupt if the memory system has partially processed a request.
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assign DelegateM = P.S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM] : MEDELEG_REGW[CauseM]) &
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assign PendingIntsM = MIP_REGW & MIE_REGW;
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assign IntPendingM = |PendingIntsM;
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assign Committed = CommittedM | CommittedF;
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assign EnabledIntsM = ({12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW);
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assign ValidIntsM = {12{~Committed}} & EnabledIntsM;
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assign InterruptM = (|ValidIntsM) & InstrValidM; // suppress interrupt if the memory system has partially processed a request.
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assign DelegateM = P.S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM] : MEDELEG_REGW[CauseM]) &
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(PrivilegeModeW == P.U_MODE | PrivilegeModeW == P.S_MODE);
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///////////////////////////////////////////
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@ -88,7 +88,7 @@ module trap import cvw::*; #(parameter cvw_t P) (
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LoadAccessFaultM | StoreAmoAccessFaultM;
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// coverage on
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assign TrapM = ExceptionM | InterruptM;
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assign RetM = mretM | sretM;
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assign RetM = mretM | sretM;
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///////////////////////////////////////////
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// Cause priority defined in table 3.7 of 20190608 privileged spec
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