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Update wallypipelinedsoc.sv

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Program clean up
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Harshini Srinath 2023-06-15 10:39:37 -07:00 committed by GitHub
parent fd00067b7f
commit 37c930bb27
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1 changed files with 3 additions and 3 deletions
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src/wally/wallypipelinedsoc.sv
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@ -51,9 +51,9 @@ module wallypipelinedsoc import cvw::*; (
output logic HREADY,
// I/O Interface
input logic TIMECLK, // optional for CLINT MTIME counter
input logic [31:0] GPIOIN, // inputs from GPIO
output logic [31:0] GPIOOUT, // output values for GPIO
output logic [31:0] GPIOEN, // output enables for GPIO
input logic [31:0] GPIOIN, // inputs from GPIO
output logic [31:0] GPIOOUT, // output values for GPIO
output logic [31:0] GPIOEN, // output enables for GPIO
input logic UARTSin, // UART serial data input
output logic UARTSout, // UART serial data output
input logic SDCCmdIn, // SDC Command input