Domenico Ottolia
1c884338b0
Forgot to add csr permission tests to testbench
2021-05-04 20:20:22 -04:00
Jarred Allen
15da77fe15
Clean up regression script and document it
2021-05-04 18:58:59 -04:00
ushakya22
6274c8cb80
Added mip tests to testbench
2021-05-04 15:36:06 -04:00
Thomas Fleming
1e0a5ef807
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-04 15:22:21 -04:00
bbracker
535046e494
small synthesis fixes
2021-05-04 15:21:01 -04:00
Thomas Fleming
37bba95500
Fix compiler warning in PMP checker
2021-05-04 15:18:08 -04:00
Domenico Ottolia
14becde792
Re-add medeleg tests to testbench
2021-05-04 14:42:20 -04:00
Ross Thompson
619dcb165d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-04 13:04:20 -05:00
Ross Thompson
2aa4db470b
Fixed synthesis bug with icache valid bit.
2021-05-04 13:03:08 -05:00
ushakya22
6a71aafadc
Updated CSR tests
2021-05-04 13:48:47 -04:00
Ross Thompson
87d3869a6e
Fixed icache pcmux control for handling miss spill miss.
2021-05-04 11:05:01 -05:00
Thomas Fleming
192878b124
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-04 03:14:38 -04:00
Thomas Fleming
dac07e34cf
Fix bug in PMP checker
...
Now we only enforce PMP regions if at least one is non-null
2021-05-04 03:14:07 -04:00
ushakya22
da352c81e7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-04 02:22:17 -04:00
ushakya22
66344f0604
Added MIE tests to testbench
2021-05-04 02:22:01 -04:00
Thomas Fleming
d7fa0903bc
Disable PMP checker to fix test loops
...
There is a bug in the PMP checker where S or U mode attempts to make a
memory access while no PMP registers are set. We currently treat this as
a failure, when this should instead be allowed.
2021-05-04 01:56:05 -04:00
Domenico Ottolia
2c39c0a6a5
Minor tweaks to mcause & scause tests
2021-05-04 01:33:49 -04:00
David Harris
7c2481bea6
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-04 01:19:57 -04:00
David Harris
4db3780ebb
Fixed testbench to produce error when signature.output doesn't exist
2021-05-04 01:19:44 -04:00
Thomas Fleming
39135f221e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-04 01:14:13 -04:00
Domenico Ottolia
1556cc5b9f
Use correct begin_signature for rv64p/MCAUSE and rv64p/SCAUSE
2021-05-04 01:04:12 -04:00
Domenico Ottolia
84911e6345
Fix 32 bit privileged tests!!!
2021-05-04 00:16:19 -04:00
Thomas Fleming
4f5ef65aeb
Restore original order of tests
2021-05-03 23:50:21 -04:00
Thomas Fleming
d53afc8510
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 23:15:39 -04:00
Thomas Fleming
1f6db293fa
Enable mmu tests in testbench
2021-05-03 23:15:23 -04:00
Domenico Ottolia
a7e89f43c1
Fix bug with IllegalInstrFaultM not getting correct value
2021-05-03 22:48:03 -04:00
Domenico Ottolia
12d8ff617b
Run all tests
2021-05-03 22:38:59 -04:00
Domenico Ottolia
353d4e9238
Update cause tests to be longer
2021-05-03 22:38:26 -04:00
Domenico Ottolia
db4e447a25
Add mtvec and stvec tests to testbench
2021-05-03 22:19:50 -04:00
Shriya Nadgauda
c10d332c6e
working testbench-imperas
2021-05-03 22:16:58 -04:00
Shriya Nadgauda
0be6b81df9
finishing merge conflict changes
2021-05-03 22:15:05 -04:00
Shriya Nadgauda
52e0b703b7
merge conflict fixes
2021-05-03 22:12:30 -04:00
Shriya Nadgauda
0282aebec7
updated pipeline tests
2021-05-03 22:07:36 -04:00
Thomas Fleming
f78f2b3b5d
Adjust attributes in PMA checker
2021-05-03 21:58:32 -04:00
David Harris
96e90402c5
Rolled back fflush on uart. Use -syncio in Modelsim command line instead.
2021-05-03 20:04:44 -04:00
David Harris
062120f944
Flush uart print statements on \n
2021-05-03 19:51:51 -04:00
David Harris
743011194b
Flush uart print statements on \n
2021-05-03 19:41:37 -04:00
David Harris
4285d60041
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 19:37:56 -04:00
David Harris
8758b6efa1
Flush uart print statements on \n
2021-05-03 19:37:45 -04:00
Elizabeth Hedenberg
08bfaeffe3
coremark print statment
2021-05-03 19:35:08 -04:00
Elizabeth Hedenberg
800f799b7c
coremark updates
2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg
81ed9b5d06
coremark directory changes
2021-05-03 19:35:06 -04:00
David Harris
2f5649832a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 19:29:01 -04:00
David Harris
1f2da4c457
Flush uart print statements on \n
2021-05-03 19:25:28 -04:00
Ross Thompson
6a01ea9f2d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 16:57:36 -05:00
Domenico Ottolia
e59f8037be
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 17:56:05 -04:00
Ross Thompson
21c0ee0cf2
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 16:56:00 -05:00
Ross Thompson
ed4f2ecb24
fixed subtle typo in icache fsm. Was messing up hit spill hit.
...
I believe the mibench qsort benchmark runs after this icache fix.
2021-05-03 16:55:36 -05:00
Domenico Ottolia
ab68933466
Fix bug that caused stvec to get the wrong value
2021-05-03 17:54:57 -04:00
Thomas Fleming
3f7061d557
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 17:38:13 -04:00
Thomas Fleming
86a93d77b4
Implement PMP checker and revise PMA checker
2021-05-03 17:37:42 -04:00
Thomas Fleming
00c3b5a033
Remove remnants of InstrReadC
2021-05-03 17:36:25 -04:00
Jarred Allen
a21b84e2ad
Add lint to regression
2021-05-03 17:32:05 -04:00
Ross Thompson
0a44d4dd4e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 14:53:54 -05:00
Ross Thompson
e09ac73eaf
Removed combinational loops between icache and PMA checker.
2021-05-03 14:51:25 -05:00
Ross Thompson
7185905f7b
Reduced icache to 1 port memory.
2021-05-03 14:47:49 -05:00
David Harris
699a8f3ac3
Extended maximum signature length to 1M
2021-05-03 15:29:20 -04:00
Katherine Parry
3f05e31954
fpu warnings fixed/commented
2021-05-03 19:17:09 +00:00
Thomas Fleming
94d734cca9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-05-03 14:02:19 -04:00
Ross Thompson
12b978fec2
Eliminated extra register and fixed ports to icache.
...
Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
2021-05-03 12:04:54 -05:00
bbracker
8ec0d18444
merge conflict resolved -- Ross and I made the same fix
2021-05-03 10:10:42 -04:00
bbracker
1db608fbc6
small rv64 plic test bugfix
2021-05-03 10:06:44 -04:00
Ross Thompson
fdf4954a20
Added back in function name to wave.do
2021-05-03 09:04:48 -05:00
Ross Thompson
b57c187208
Fixed typo in ifu for bypassing branch predictor.
...
Fixed missing signal name in local history predictor.
2021-05-03 08:56:45 -05:00
David Harris
c9806fb472
Fixed lint error in div
2021-05-03 09:26:12 -04:00
bbracker
fb0910d9c0
ifu lint fixes
2021-05-03 09:25:22 -04:00
bbracker
acd99be7f8
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 09:23:52 -04:00
Noah Boorstin
8d417558ae
busybear: remove now unneeded hack for fixed CSR issue
2021-05-01 15:17:04 -04:00
Katherine Parry
9252d08b41
fpu imperas tests run
2021-05-01 02:18:01 +00:00
bbracker
0d62440f60
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-30 06:26:35 -04:00
bbracker
9c08ce5359
rv32 plic test and lint fixes
2021-04-30 06:26:31 -04:00
Noah Boorstin
c9fcd3405d
rollback regression to 400k instrs for busybear
2021-04-29 20:59:30 -04:00
Domenico Ottolia
830787e3e1
Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts
2021-04-29 20:42:14 -04:00
Ross Thompson
893e03d55b
Fixed memory size in configs for rv32ic and rv64ic.
...
Removed warning on call to $fscanf.
2021-04-29 17:36:46 -05:00
Domenico Ottolia
750d276feb
Minor improvements to scause test
2021-04-29 16:48:07 -04:00
Domenico Ottolia
fdbd238a87
Add machine-mode timer interrupts to mcause tests
2021-04-29 16:39:18 -04:00
Thomas Fleming
10c7260980
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-29 16:30:00 -04:00
Domenico Ottolia
c9cb2f51d1
Same but don't break sim-wally this time
2021-04-29 15:33:27 -04:00
Domenico Ottolia
fdd4deec2f
Add more exceptions to medeleg tests
2021-04-29 15:32:13 -04:00
ushakya22
de23edcfb9
fix to pcm bug
2021-04-29 15:21:08 -04:00
ushakya22
f139f248dc
Working MIE timer tests
2021-04-29 15:19:43 -04:00
Domenico Ottolia
99a927be47
Add medeleg tests
2021-04-29 15:02:36 -04:00
Jarred Allen
246b41e604
Enhance lint-wally functionality
2021-04-29 14:48:41 -04:00
Jarred Allen
c6996ce39d
Remove signal which no longer exists from default waves, so sim-wally works
2021-04-29 14:41:10 -04:00
Jarred Allen
000f48cd75
Fix compile error in branch predictor
2021-04-29 14:36:56 -04:00
Shreya Sanghai
b554dc8e72
fixed bug in gshare, global and local history BP
2021-04-29 06:14:32 -04:00
Thomas Fleming
e091f430e0
Clean up PMA checker and begin PMP checker
2021-04-29 02:20:39 -04:00
Thomas Fleming
d29ddddc3f
Remove unused waves from .do files
2021-04-29 02:19:46 -04:00
Thomas Fleming
6515c0b9ed
Add mmu waves (commented) to busybear
2021-04-28 20:01:05 -04:00
Noah Boorstin
9275f141f9
same but do that right this time
2021-04-28 14:27:28 -04:00
Domenico Ottolia
1c30625382
Modify make file to make privileged tests always pass Imperas (for testing interrupts) & Add mtvec/stvec tests
2021-04-27 21:47:38 -04:00
Noah Boorstin
fce3d6a8b1
busybear: respect branch predictor disable config
2021-04-27 15:52:18 -04:00
Ross Thompson
d191bc6cc1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-26 14:28:09 -05:00
Ross Thompson
14a69c1d06
Added the ability to exclude branch predictor.
2021-04-26 14:27:42 -05:00
Noah Boorstin
922c8e450f
ok but do that better
2021-04-26 14:38:05 -04:00
Noah Boorstin
24bbb674d3
linux: start using internal branch predictor signal
2021-04-26 14:34:38 -04:00
Ross Thompson
a7e4d39ea1
Fixed issue with not saving the first cache block read on a miss spill.
2021-04-26 12:57:34 -05:00
Noah Boorstin
9cbc769083
minor busybear fixes
2021-04-26 13:24:39 -04:00
Ross Thompson
44d28dbd1c
Icache integrated!
...
Merge branch 'icache-almost-working' into main
2021-04-26 11:48:58 -05:00
Ross Thompson
615831f588
Reverted back the exe2memfile.pl script changes. Something I changed broke the load tests.
2021-04-26 10:44:27 -05:00
