Ross Thompson 12b978fec2 Eliminated extra register and fixed ports to icache. ... Still need to support physical tag check and write in icache memory. Still need to reduce to 1 port SRAM in icache. I would like to refactor the icache code.		2021-05-03 12:04:54 -05:00
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bin	Icache integrated!	2021-04-26 11:48:58 -05:00
config	Fixed memory size in configs for rv32ic and rv64ic.	2021-04-29 17:36:46 -05:00
misc/tlb_toy	Various code syntax changes to bring HDL to a synthesizable level	2021-04-13 11:27:12 -05:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	Eliminated extra register and fixed ports to icache.	2021-05-03 12:04:54 -05:00
src	Eliminated extra register and fixed ports to icache.	2021-05-03 12:04:54 -05:00
testbench	busybear: remove now unneeded hack for fixed CSR issue	2021-05-01 15:17:04 -04:00
testgen	Add machine-mode timer interrupts to mcause tests	2021-04-29 16:39:18 -04:00
lint-wally	Enhance lint-wally functionality	2021-04-29 14:48:41 -04:00