Rose Thompson
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a885240fbd
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temporary commit to help debug merging testbench.sv with testbench-imperas.sv
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2024-05-17 12:36:00 -05:00 |
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Rose Thompson
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bd8450734b
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Fixed more bugs with wally.do.
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2024-05-17 10:39:00 -05:00 |
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Rose Thompson
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46e6459965
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Updated script to run linux with imperasDV.
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2024-05-14 13:46:27 -05:00 |
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Rose Thompson
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970af9551c
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Fixed bug with gui mode testbench_fp
removed old wally-linux-imperas.do
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2024-05-14 13:41:20 -05:00 |
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Rose Thompson
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30bea18dec
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Maybe have imperasDV linux simulation merged into wally.do
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2024-05-14 12:38:19 -05:00 |
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Rose Thompson
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e8f5545076
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Got imperasDV running linux simulation again.
Now need to merge do files.
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2024-05-13 16:43:13 -05:00 |
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Rose Thompson
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ceb31fec68
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2024-05-10 08:54:23 -05:00 |
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Rose Thompson
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b027fa44ef
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2024-05-10 08:53:00 -05:00 |
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Rose Thompson
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93ea5b0c1e
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Fixed wavefile to have function logger.
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2024-05-10 08:50:42 -05:00 |
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David Harris
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04457d49f7
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Updated sim-testfloat-verilator to use wsim
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2024-05-10 05:03:24 -07:00 |
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David Harris
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61e559606e
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Fixed wsim to be able to invoke TestFloat with Verilator. However, TestFloat produces incorrect results with Verilator
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2024-05-09 18:56:59 -07:00 |
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David Harris
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0d1d59a3d8
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2024-05-08 18:58:01 -07:00 |
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Divya2030
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eff2264752
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Code Coverage Text format for each test and configuration in IndividualCovReport
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2024-05-08 05:24:24 -07:00 |
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Divya2030
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b4b88c5858
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VCS regression & Code Coverage
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2024-05-08 04:39:42 -07:00 |
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Divya2030
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31ae18922b
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regression_wally vcs run works
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2024-05-08 04:25:03 -07:00 |
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David Harris
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927f166e1f
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2024-05-07 12:58:40 -07:00 |
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Divya2030
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a3f1a274d2
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VCS Simulation Passed
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2024-05-07 10:41:02 -07:00 |
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David Harris
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37fc45cd35
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Updated Questa wally.do to terminate on a compile error
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2024-05-06 11:28:00 -07:00 |
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Divya2030
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48ad4d6001
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pmp coverage
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2024-05-02 11:52:54 -07:00 |
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Divya2030
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3853f94337
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Revert "initial commit pmp basic coverage working"
This reverts commit 7ca1c976c0.
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2024-05-02 11:23:59 -07:00 |
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Divya2030
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7ca1c976c0
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initial commit pmp basic coverage working
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2024-05-02 10:33:29 -07:00 |
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Kunlin Han
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cde284d003
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Fix the problem of missing sim/verilator/wkdir
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2024-04-30 10:48:42 -07:00 |
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David Harris
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8f0c68373e
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Verilator fulladder example improvmeents
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2024-04-28 22:08:00 -07:00 |
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David Harris
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1274ec55af
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Resolved merge conflict
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2024-04-26 16:15:23 -07:00 |
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Quswar Abid
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f999ccadf4
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/cad/mentor/questa_sim-2023.4/questasim is fixed, relative paths to design and testbench files are fixed, and RISCV-DV submodule is updated back to the latest commit on master branch
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2024-04-26 15:55:39 -07:00 |
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David Harris
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5d97858806
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Moved functional coverage files to sim/questa and to tests/riscvdv
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2024-04-24 11:46:38 -07:00 |
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David Harris
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5f3676dfd7
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Merge pull request #753 from quswarabid/riscvdv_bringup
RISCVDV bringup - Coverage Collection on RISCVISACOV
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2024-04-24 09:47:34 -07:00 |
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Quswar Abid
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7b441d2881
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Bringup of RISCV-DV to collect functional coverage - Update to track RV64IMAFDC_Zicsr related coverpoints from riscvISACOV
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2024-04-23 18:20:29 -07:00 |
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David Harris
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0dc2c7d16a
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Fixed deriv path in Verilator makefile
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2024-04-23 10:19:08 -07:00 |
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David Harris
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f9eec8c43f
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Merged wsim changes
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2024-04-22 13:11:35 -07:00 |
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Kunlin Han
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9be0303493
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Add support for dumping vcd.
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2024-04-22 13:03:51 -07:00 |
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David Harris
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cc236bdb25
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Resolved merge conflicts
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2024-04-22 12:16:06 -07:00 |
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Kunlin Han
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c134b712c4
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Merge branch 'main' into verilator
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2024-04-22 11:35:18 -07:00 |
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Kunlin Han
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c383bef1ad
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Run verilator configurations and testsuites in different folders.
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2024-04-22 11:32:46 -07:00 |
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David Harris
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45196a9959
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ignore VCS junk files
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2024-04-21 19:49:55 -07:00 |
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David Harris
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00a1c0fc57
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Fixed WALLY/RISCV paths in testbench/rom1p1r; search log files for warnings and errors
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2024-04-21 00:02:15 -07:00 |
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David Harris
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fd6a6b2249
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environment variable cleanup
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2024-04-20 22:52:08 -07:00 |
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David Harris
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a1876b1e7c
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script cleanup
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2024-04-20 17:22:31 -07:00 |
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David Harris
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571b67f565
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Merging PR738
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2024-04-20 17:15:17 -07:00 |
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slmnemo
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6458fa5642
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Merge branch 'main' of https://github.com/openhwgroup/cvw into linux_nightly
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2024-04-20 14:46:35 -07:00 |
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David Harris
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3cb5cd0cb1
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simulator cleanup
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2024-04-20 14:12:55 -07:00 |
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David Harris
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c8e7a6990d
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2024-04-20 11:44:27 -07:00 |
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David Harris
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bf2f6859e4
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Changed Verilog makefile to print transcript to stdout by default like Questa; redirected to logfile elsewhere
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2024-04-20 11:27:54 -07:00 |
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David Harris
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84e8d86d2a
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Merge pull request #739 from Karl-Han/deriv_support
Add extra path to search for deriv/buildroot
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2024-04-20 11:23:54 -07:00 |
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slmnemo
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2b0cf90a99
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Merged with merge conflict
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2024-04-17 10:47:28 -07:00 |
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Kunlin Han
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91a88fa46c
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Update sim/verilator/Makefile with more comments and merging variables.
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2024-04-17 09:52:54 -07:00 |
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Kunlin Han
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392eedb342
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Update sim/verilator/Makefile with constants for simplicity.
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2024-04-16 18:54:11 -07:00 |
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Kunlin Han
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6f6b1fd1fd
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Add extra path to search for deriv/buildroot.
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2024-04-16 18:45:21 -07:00 |
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slmnemo
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554f818a8c
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Fixed wave.do to match new conditional generate block names
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2024-04-16 14:43:38 -07:00 |
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Rose Thompson
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dd3460c1a9
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Fixed makefile and regression-wally so that code coverage now works.
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2024-04-16 15:44:42 -05:00 |
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