David Harris
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c6631ef808
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Added N and PBMT bits to MMU PTE
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2023-08-24 19:44:46 -07:00 |
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David Harris
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f5dab9f2fe
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Check for legal SATP mode values
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2023-08-24 05:18:04 -07:00 |
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Ross Thompson
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00e65c4ae7
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Oups there was a bug in the SATP fix. RV32GC was broken by the changes.
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2023-08-23 09:42:46 -05:00 |
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Ross Thompson
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45a7dfba28
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-08-23 09:15:13 -05:00 |
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Jacob Pease
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140d246fb5
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Prevented writes to SATP enabling SV57. This follows the spec more accurately. Linux can now successfully probe SATP.
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2023-08-22 16:25:56 -05:00 |
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Ross Thompson
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c2a9fbb1fc
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Fixed bug with the cbo.inval clearing already cleared lines.
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2023-08-21 17:51:51 -05:00 |
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Ross Thompson
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05d590b0b9
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Fixed issue when with flush miss.
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2023-08-18 16:36:13 -05:00 |
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Ross Thompson
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fc3fccafe9
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Now we have invalidate, clean, and flush working.
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2023-08-18 16:32:22 -05:00 |
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Ross Thompson
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4eeba9bed9
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Added cbom test to custom. Needs to be moved to wally-riscv-arch-tests.
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2023-08-18 15:59:39 -05:00 |
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Ross Thompson
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5c408454b8
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Might have working cbo clean and flush instructions.
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2023-08-18 14:48:21 -05:00 |
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Ross Thompson
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21129dde71
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Fixed cbo instruction decode.
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2023-08-18 11:32:30 -05:00 |
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Ross Thompson
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9dcc70d6c1
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Updated the hazard logic for CMO operations.
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2023-08-17 17:58:49 -05:00 |
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Ross Thompson
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072126b967
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Found first bug in CMO implementation.
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2023-08-17 16:57:54 -05:00 |
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Ross Thompson
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f9df1fda23
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CMOZ now implemented in the D cache.
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2023-08-17 12:46:40 -05:00 |
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Ross Thompson
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624b3e3ab2
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Added clean and flush to cache fsm.
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2023-08-16 14:23:56 -05:00 |
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Ross Thompson
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5281077531
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More progress towards cmo.
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2023-08-15 18:17:15 -05:00 |
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Ross Thompson
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9f37fef145
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The L1 D cache now supports cache line (block) invalidation and partial support for clean and flush.
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2023-08-14 16:39:18 -05:00 |
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Ross Thompson
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0eac74ac7b
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Initial CMO implementation. Just adds control signals into the L1 caches.
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2023-08-14 15:43:12 -05:00 |
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Ross Thompson
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7a196d3fa7
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Cache cleanup.
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2023-07-31 14:12:53 -05:00 |
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Ross Thompson
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faaf43fa10
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Merge pull request #372 from davidharrishmc/dev
PLIC part select warnings fixed
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2023-07-31 11:28:28 -04:00 |
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David Harris
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6ff2b0cc2c
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Merge pull request #373 from harshinisrinath1001/main
Improved testing of pmd in priv, fixed bugs, and attempted to reset menvcfg and fixed spacing in fpu/fma and fpu/postprocessing
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2023-07-30 22:46:44 -07:00 |
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Harshini Srinath
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7ed4cf97ed
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Fixed formatting
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2023-07-30 18:36:25 -07:00 |
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Harshini Srinath
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603ed2160e
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Fixed formatting
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2023-07-30 18:30:23 -07:00 |
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Harshini Srinath
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acbbe7941a
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Fixed formatting
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2023-07-30 18:27:22 -07:00 |
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Harshini Srinath
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e4de9ae87c
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Fixed formatting
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2023-07-30 18:18:24 -07:00 |
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Harshini Srinath
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4c1a07eb9c
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Fixed formatting
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2023-07-30 18:06:25 -07:00 |
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Harshini Srinath
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1badc8a8c5
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Fixed formatting
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2023-07-30 18:00:39 -07:00 |
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Harshini Srinath
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41555b149e
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Fixed formatting
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2023-07-30 17:54:47 -07:00 |
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Harshini Srinath
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8e97224cd7
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Fixed formatting
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2023-07-30 17:46:23 -07:00 |
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Harshini Srinath
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469b03577d
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Fixed formatting
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2023-07-30 17:39:37 -07:00 |
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Harshini Srinath
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141384f60f
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Fixed formatting
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2023-07-30 17:38:22 -07:00 |
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Harshini Srinath
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bbbd5f6b2d
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Fixed spacing
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2023-07-30 17:32:46 -07:00 |
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Harshini Srinath
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d7b2d84124
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Fixed spacing
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2023-07-30 17:22:40 -07:00 |
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Harshini Srinath
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b129068a92
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Fixed spacing
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2023-07-30 17:21:52 -07:00 |
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Harshini Srinath
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49823ccd45
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Fixed spacing
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2023-07-30 17:21:22 -07:00 |
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Harshini Srinath
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36108e4b52
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Fixed spacing
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2023-07-30 17:18:25 -07:00 |
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Harshini Srinath
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d88b2fd9c1
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Fixed spacing
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2023-07-30 16:59:27 -07:00 |
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Harshini Srinath
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d69d0ececc
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Fixed spacing
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2023-07-30 16:57:57 -07:00 |
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David Harris
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d58ece3d44
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renamed test-shared.vh to config-shared.vh
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2023-07-30 05:22:39 -07:00 |
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David Harris
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28823aca6e
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Cleaned up lint for plic_apb part select
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2023-07-30 02:00:38 -07:00 |
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David Harris
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654cafb7f7
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Fixed Questa warnings in plic_apb about part select out of bounds
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2023-07-30 01:54:41 -07:00 |
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Ross Thompson
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7e06775135
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Fixed a very subtle combinational loop bug the SSTC implementation of csrs.sv. STIMCMPH did not assign all XLEN bits of CSRSReadValM so dc_shell produced d-latches and vivado created a combinational loop.
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2023-07-28 11:20:29 -05:00 |
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Ross Thompson
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15dc76310e
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Fixed lint errors for issue #368. Does not fix simulation errors. We made a design decision a long time ago to not support DTIM on the rv32gc config because LLEN was greater than XLEN.
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2023-07-26 15:08:01 -05:00 |
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Ross Thompson
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2dac02c14c
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-07-25 15:13:07 -05:00 |
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David Harris
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ca62487e4c
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Formatting cleanup
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2023-07-25 05:11:38 -07:00 |
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Ross Thompson
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b1f7a5768f
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Removed all old references to the old flash card controller.
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
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2023-07-24 15:45:57 -05:00 |
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Ross Thompson
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63afd95ad3
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Fixed bugs in boot and new flash card merge. Works with arty a7 now.
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2023-07-22 15:52:25 -05:00 |
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Ross Thompson
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a89a1e675c
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Merge branch 'boot' into mergeBoot
Merges Jacob's new sdc controller into wally.
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2023-07-21 17:43:45 -05:00 |
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Ross Thompson
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f895898d22
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Improved the critical path even more. The Arty A7 works upto 19Mhz easily. Testing out 22Mhz now.
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2023-07-21 16:31:26 -05:00 |
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Ross Thompson
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d04d2afed2
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Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card.
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2023-07-21 13:06:27 -05:00 |
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