Ross Thompson
5e5ca0809f
Removed more *** from lsu and updated assertions for dtim.
2024-06-19 10:52:51 -07:00
David Harris
4a4bbdfc43
More code cleanup
2024-06-14 09:50:07 -07:00
David Harris
53477b2c85
Code cleanup
2024-06-14 07:08:17 -07:00
David Harris
b1c9450b4a
Code cleanup: RAM, fdivsqrt
2024-06-14 03:35:05 -07:00
David Harris
312c9c9f55
Updated logger to new IClass signal name
2024-06-12 07:24:05 -07:00
Rose Thompson
9a42aab971
Merge pull request #804 from jordancarlin/dev
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Eliminate more logical operators and replace with bitwise operators
2024-05-16 15:45:18 -05:00
Jordan Carlin
1d8ffee20c
Certain Zcb instructions are dependent on other extensions, not the entire extension
2024-05-15 19:16:43 -07:00
Jordan Carlin
ef778da98d
Eliminate more logical operators and replace with bitwise
2024-05-15 10:50:23 -07:00
Jordan Carlin
4ffce9a752
Switch riscvassertions to use bitwise operators instead of logical operators per Wally style guide
2024-05-15 09:23:24 -07:00
Jordan Carlin
291d1e62d5
M implies Zmmul
2024-05-14 19:38:34 -07:00
Jordan Carlin
4a72922087
update config to derive MISA from macros
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- Remove C_SUPPORTED and update decompress unit based on Zc* extensions
- Derive A_SUPPORTED from A subextensions
- Derive B_SUPPORTED from B subextensions
- Derive C_SUPPORTED from C subextensions
2024-05-14 06:49:18 -07:00
David Harris
77137f0f60
ZAAMO and ZALRSC implemented but not tested
2024-05-07 16:45:49 -07:00
David Harris
9b22275438
Removed unused signals from WallyTracer
2024-04-30 08:54:28 -07:00
David Harris
a1876b1e7c
script cleanup
2024-04-20 17:22:31 -07:00
David Harris
ac9a21873d
Pass TEST to testbench with +TEST=<name> rather than -G TEST=<name> so that we don't have to recompile for every new test
2024-04-06 10:34:21 -07:00
Rose Thompson
081cf5be55
Fixed the CacheHit logger bug.
2024-03-28 13:40:01 -05:00
Kunlin Han
22b59138f0
Remove all #delay from non-testbench.
2024-03-16 11:20:32 -07:00
Kunlin Han
8c67a76912
Remove all #delay from non-testbench.
2024-03-13 10:31:40 -07:00
David Harris
2580d37fc0
ZK cleanup, check no LLEN > XLEN without D$, add half and quad float load/store to instruction name decoder
2024-03-10 22:03:57 -07:00
Rose Thompson
3cf6a19729
Merge branch 'main' into main
2024-03-10 10:48:21 -05:00
Rose Thompson
e870e8137b
Finished Wally rvvi tracer.
2024-03-08 09:16:30 -06:00
David Harris
b386331cc8
Changed '0 to 0 where possible per Chapter 4 style guidelines
2024-03-06 05:48:17 -08:00
KelvinTr
01c45ab9d7
Fixed K extension changes
2024-02-28 17:05:08 -06:00
David Harris
efdc571f59
Removed redundant assertion
2024-02-01 20:14:40 -08:00
David Harris
49714cb282
Fixed assertions to throw fatal error, improved nightly regression to have passing cases
2024-01-31 21:39:18 -08:00
David Harris
74b242ce5c
Partial implementation of fcvtmod.w.d; flags disagree in one case where Sail might be wrong, and result 134 is wrong because of overflow
2024-01-17 12:25:06 -08:00
David Harris
da4eca4854
Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int.
2024-01-15 13:24:57 -08:00
David Harris
9eb6d9c8b8
Added Zicond support
2024-01-11 07:37:15 -08:00
Rose Thompson
408bb2c35b
Yay! I got verilator to compile our testbench! Does it actually work I don't know.
2023-12-18 16:44:34 -06:00
Rose Thompson
0f7b6ada04
Cleanup.
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Verilator still has issues with riscassertions.sv and the testbench
2023-12-18 16:38:56 -06:00
Rose Thompson
b7b245fe2f
functionName.sv is now linting for rv64gc.
2023-12-18 16:37:26 -06:00
Rose Thompson
c1ac153a4f
Closer to verilator support.
2023-12-18 16:26:56 -06:00
Rose Thompson
58942b246b
Kind of a frustrating set of changes to get the verilator errors out of the copyShadow module.
2023-12-18 13:34:14 -06:00
Rose Thompson
4a3cc8b9c8
More progress towards verilator.
2023-12-18 13:26:43 -06:00
Rose Thompson
5062a8c89c
Added parameter for cache's SRAM length.
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Progress towards verilator support.
2023-12-18 12:50:49 -06:00
David Harris
aff61ea97a
Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator
2023-12-13 11:33:59 -08:00
David Harris
3df4c13daa
Updated wallyTracer for Linux boot and wally-batch.do to remove buildroot checkpoint support
2023-11-23 20:36:45 -08:00
David Harris
1f57df7f8b
Fixed reference to deleted atomic signal in cache
2023-11-23 20:29:10 -08:00
Rose Thompson
1dac4d221e
Disable the trace for normal operation.
2023-11-21 13:49:07 -06:00
Rose Thompson
c77a47b403
Output the instruction trace to the logs directory.
2023-11-21 13:47:58 -06:00
Rose Thompson
b02bd6c835
Finally we got the wally tracer working with linux.
2023-11-21 13:45:55 -06:00
Rose Thompson
3fd6d3464c
We are logging now.
2023-11-21 13:02:34 -06:00
Rose Thompson
6ff8d19157
Added code to the wallyTracer to support outputing an instruction trace.
2023-11-21 12:28:19 -06:00
Rose Thompson
bc935b1b3b
Fixed second bug in the logger script when branch logging enabled but counter logger not.
2023-11-15 14:56:02 -06:00
Rose Thompson
5d4a89b27c
Fixed bug in the btb branch logging.
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We were only logging branch instructions not all control flow instructions which dramatically skewed the results for sim_bp.
2023-11-15 14:51:47 -06:00
Rose Thompson
540d8d930d
Cleanup.
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Linux makefile
wally tracer. probably reduce some complexity here.
2023-11-13 14:04:43 -06:00
David Harris
bddd2d573e
Shortened path to PCSrcE in logger to avoid problematic hierarchical reference
2023-11-05 07:06:53 -08:00
David Harris
568aa3c4a6
Verilator improvements
2023-11-04 03:21:07 -07:00
David Harris
09aebbf252
Fixed regression error of watchdog timeout when PCM is optimized out of the IFU
2023-11-03 04:38:27 -07:00
Ross Thompson
fc83f33615
Oups. When fixing the linux-imperasdv testbench I accidentally introduced a bug to the tracer.
2023-10-05 13:00:46 -05:00
