David Harris 568aa3c4a6 Verilator improvements		2023-11-04 03:21:07 -07:00
..
checksignature.sv	Significant refactoring of testbench.	2023-06-14 17:02:49 -05:00
DCaacheFlushFSM.sv	Verilator improvements	2023-11-04 03:21:07 -07:00
functionName.sv	Merge branch 'main' of github.com:ross144/cvw into main	2023-07-11 15:08:26 -05:00
instrNameDecTB.sv	Added logic to warn about x in memory reads. Added cbo instruction names to testbench decoder	2023-07-02 13:29:27 -07:00
instrTrackerTB.sv	moved riscvassertons to its own file, added proper license headers to testbench support files	2023-02-16 19:40:27 -08:00
loggers.sv	Fixed the icache and dcache overlogging issue.	2023-07-14 15:47:05 -05:00
ramxdetector.sv	Added logic to warn about x in memory reads. Added cbo instruction names to testbench decoder	2023-07-02 13:29:27 -07:00
riscvassertions.sv	Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there	2023-10-04 12:28:12 -07:00
wallyTracer.sv	Oups. When fixing the linux-imperasdv testbench I accidentally introduced a bug to the tracer.	2023-10-05 13:00:46 -05:00
watchdog.sv	Fixed regression error of watchdog timeout when PCM is optimized out of the IFU	2023-11-03 04:38:27 -07:00