Rose Thompson e870e8137b Finished Wally rvvi tracer.		2024-03-08 09:16:30 -06:00
..
checksignature.sv	Significant refactoring of testbench.	2023-06-14 17:02:49 -05:00
DCacheFlushFSM.sv	Closer to verilator support.	2023-12-18 16:26:56 -06:00
functionName.sv	Changed '0 to 0 where possible per Chapter 4 style guidelines	2024-03-06 05:48:17 -08:00
instrNameDecTB.sv	Partial implementation of fcvtmod.w.d; flags disagree in one case where Sail might be wrong, and result 134 is wrong because of overflow	2024-01-17 12:25:06 -08:00
instrTrackerTB.sv	moved riscvassertons to its own file, added proper license headers to testbench support files	2023-02-16 19:40:27 -08:00
loggers.sv	Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator	2023-12-13 11:33:59 -08:00
ramxdetector.sv	Yay! I got verilator to compile our testbench! Does it actually work I don't know.	2023-12-18 16:44:34 -06:00
riscvassertions.sv	Removed redundant assertion	2024-02-01 20:14:40 -08:00
wallyTracer.sv	Finished Wally rvvi tracer.	2024-03-08 09:16:30 -06:00
watchdog.sv	Changed '0 to 0 where possible per Chapter 4 style guidelines	2024-03-06 05:48:17 -08:00