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2134 Commits

Author SHA1 Message Date
Ross Thompson
5b740fbf60 Removed SDC from repo due to copy right issue. 
Modified fpga build flow to reference it outside the repo.
 2023-01-20 14:57:06 -06:00
Ross Thompson
b1f3bd566c Formatting. 2023-01-20 13:13:05 -06:00
Ross Thompson
f78bfc4940 Formatting. 2023-01-20 13:09:42 -06:00
Ross Thompson
c7f4970597 Formatting. 2023-01-20 13:05:10 -06:00
Ross Thompson
6142c96946 Reformatting cachefsm. 2023-01-20 12:49:55 -06:00
Ross Thompson
7e96f3e8f7 Formatting. 2023-01-20 12:41:57 -06:00
Ross Thompson
95de716a17 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-20 12:37:12 -06:00
Ross Thompson
b8a699270e More cleanup and formatting. 2023-01-20 12:34:40 -06:00
David Harris
032332ebae renamed comparator module 2023-01-20 10:13:47 -08:00
Ross Thompson
f1049be6c1 More cleanup and formatting. 2023-01-20 12:09:21 -06:00
Ross Thompson
4a2d02ab28 Formatting. 2023-01-20 11:51:10 -06:00
Ross Thompson
11c44006c4 Integrated the missing zifence tests into the regression test. 2023-01-20 10:34:49 -06:00
Ross Thompson
eb19b1b499 Imperas found a bug with the Fence.I instruction. 
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold.  This cause the d$ flush to go high while in ReadHold.  The solution is
to ensure the cache continues to assert Stall while in WriteLine state.

There was a second issue also.  The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
 2023-01-20 10:17:21 -06:00
Ross Thompson
6f3b8680d5 Imperas found a bug with the Fence.I instruction. 
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold.  This cause the d$ flush to go high while in ReadHold.  The solution is
to ensure the cache continues to assert Stall while in WriteLine state.

There was a second issue also.  The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
 2023-01-20 09:41:18 -06:00
Ross Thompson
63dbebcb5a Improved comment. 2023-01-19 17:41:57 -06:00
Ross Thompson
91bd55d9ba ram uses always rather than always_ff due to modelsim issue. 2023-01-19 17:41:15 -06:00
Ross Thompson
30935fd2b7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-19 17:28:53 -06:00
Ross Thompson
78e8598ec8 Added comment about needed changes in BTB. 2023-01-19 17:28:00 -06:00
David Harris
aed6f79d1e Removed study versions from comparator 2023-01-19 15:13:35 -08:00
David Harris
ad3b528b5d Moved unused study files to studies directory 2023-01-19 15:13:11 -08:00
David Harris
264362ce17 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-19 14:47:54 -08:00
David Harris
a1b25e1039 RAM declaration cleanup: 2023-01-19 14:47:51 -08:00
Ross Thompson
75391f4b56 Formatting. 2023-01-19 15:06:37 -06:00
Ross Thompson
40d62ec0d1 Formatting. 2023-01-19 14:18:46 -06:00
Ross Thompson
999477bb02 Formatting and name changes. 2023-01-19 14:16:29 -06:00
eroom1966
43d5769bd9 update 2023-01-19 13:29:46 +00:00
Ross Thompson
0bbf6e4ae2 Formatting. 2023-01-18 19:26:20 -06:00
Ross Thompson
21b2b10e78 Formatting spillsupport. 2023-01-18 19:25:54 -06:00
Ross Thompson
db48e547f0 Formatting. 2023-01-18 19:11:30 -06:00
Ross Thompson
9170827c98 Reduced complexity of spill logic by ensuring the irom outputs offset instrutions on a spill. 2023-01-18 19:10:34 -06:00
Ross Thompson
e79c403fe1 More IROM cleanup. 2023-01-18 18:47:02 -06:00
Ross Thompson
63577cbf4a Cleanup dtim and irom. 2023-01-18 18:44:30 -06:00
Ross Thompson
2d945963e6 Added comments to decompress.sv. May want to consider additional documentation. 2023-01-18 18:26:51 -06:00
Ross Thompson
f34c67722d Formatted subword* and bytemask. 2023-01-18 18:20:22 -06:00
Ross Thompson
f288b9ca14 Formatting. 2023-01-18 18:17:48 -06:00
Ross Thompson
cc186d0f3b Formatting. 2023-01-18 18:16:56 -06:00
Ross Thompson
a8549f26f2 Formatting. 2023-01-18 18:16:20 -06:00
Ross Thompson
cca6146dab Renamed signals in amoalu. 2023-01-18 18:13:18 -06:00
Ross Thompson
b223e22642 Formatting. 2023-01-18 18:05:11 -06:00
Ross Thompson
a5450c27ab Formatting. 2023-01-18 17:56:47 -06:00
Ross Thompson
87f2133d91 Formatting. 2023-01-18 17:49:19 -06:00
Ross Thompson
4e882e0769 Formating. 2023-01-18 17:30:08 -06:00
Ross Thompson
92f04f055c Formatting 2023-01-18 17:14:37 -06:00
Ross Thompson
520209363d Formatting 2023-01-18 17:03:45 -06:00
Ross Thompson
c5c4a3c011 Formatting 2023-01-18 16:58:03 -06:00
Ross Thompson
edc4630742 Formating. 2023-01-18 16:52:46 -06:00
Ross Thompson
32589a5efc Formating. 2023-01-18 16:47:40 -06:00
David Harris
d1ad6b464d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-18 13:07:03 -08:00
David Harris
a96d8dcec0 removed fma directory, improved plic comments 2023-01-18 13:06:54 -08:00
eroom1966
8dea3491a3 Partial fix for misaligned LD/ST 2023-01-18 17:11:39 +00:00
eroom1966
0ccab9accc changes made with Ross 2023-01-18 16:46:48 +00:00
sarah-harris
75038c279d Minor fixes in datapath.sv and ieu.sv (comments, putting signals in correct grouping) 2023-01-18 07:26:08 -08:00
eroom1966
247879e7c7 add im flags for compressed disass 2023-01-18 13:37:28 +00:00
eroom1966
52ebac59b8 remove volatile for FFLAGS and FCSR 2023-01-18 13:33:57 +00:00
eroom1966
68af12ece1 refer to correct path 2023-01-18 13:26:07 +00:00
Ross Thompson
c02195301b More comments added to abhfsm. 2023-01-17 22:58:06 -06:00
Ross Thompson
36acc91b67 formating ahbinterface. 2023-01-17 22:54:42 -06:00
Ross Thompson
93fb8db9bb Moved amoalu to lsu. 2023-01-17 22:45:46 -06:00
Ross Thompson
cd5e62119a Added commenets and formating to abhcachefsm and abhcacheinterface. 2023-01-17 22:22:23 -06:00
Ross Thompson
c3096eea2a Cleaned up ahbcacheinterface. 2023-01-17 22:13:56 -06:00
Ross Thompson
4720b28272 Formatting progress. 2023-01-17 22:10:31 -06:00
Ross Thompson
d21eef40d7 Added comments to dtim and ahbcacheinterface. 2023-01-17 21:56:55 -06:00
Ross Thompson
42d0e1f8d2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-17 21:54:55 -06:00
Ross Thompson
374f95ebf3 Fixed the rvvi CSR write enable not synchronized with a valid instruction in the Writeback stage. 2023-01-17 18:24:46 -06:00
Ross Thompson
8f5b5e0989 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2023-01-17 15:44:44 -06:00
David Harris
fd52915f3c Clean up warnings from Questa 2023-01-17 13:43:39 -08:00
Ross Thompson
b2676e1dd4 Somehow the imperas files spilled into the main branch. 2023-01-17 15:39:34 -06:00
Ross Thompson
01f3432f6e Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-17 14:50:45 -06:00
David Harris
4a01ebd4d9 IEU comment cleanup 2023-01-17 10:51:44 -08:00
David Harris
e0dbbb60c9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-17 06:47:06 -08:00
David Harris
cd281996a0 IEU signal comment cleanup 2023-01-17 06:47:02 -08:00
sarah-harris
9fb7c8132a Changing signal name to ImmExtD/E to match figures 
Changing signal name:
ExtImmD/E -> ImmExtD/E

to match figures.
 2023-01-17 06:33:58 -08:00
David Harris
2c00ac5254 pipelined/src/ieu/ieu.sv 2023-01-17 06:08:26 -08:00
sarah-harris
3124ebc3e1 IEU cleanup 
IEU cleanup
 2023-01-17 06:02:26 -08:00
eroom1966
cf3223df22 refactor all rvvi into single initial block 2023-01-17 13:01:01 +00:00
eroom1966
2ead2cdaf4 Code refactor and addition of rvvi interface 2023-01-17 12:47:38 +00:00
Ross Thompson
79c9e4df12 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-16 14:03:05 -06:00
Ross Thompson
1680f89ef3 Found a potential issue with mstatush when XLEN = 64. 2023-01-16 13:57:28 -06:00
Ross Thompson
7984194c2a Fixed issue with rvvi tracer so it reports call csr changes, not just instrutions which write the CSRs. 2023-01-16 13:35:06 -06:00
David Harris
3e17bfbc53 Removed Imperas tests from regression 2023-01-16 07:01:07 -08:00
David Harris
fdb839edcb Makefile and setup cleanup 2023-01-15 20:27:12 -08:00
David Harris
dc74bcff5b Clean up tabs 2023-01-15 18:23:09 -08:00
Ross Thompson
4e1e10a729 Fixed bug with gshare repair from branch class miss prediction. 2023-01-15 14:39:48 -06:00
David Harris
364cf97c34 cache cleanup 2023-01-14 19:43:29 -08:00
David Harris
94d01d292e ebu cleanup 2023-01-14 19:29:45 -08:00
David Harris
17fd2d2a3b ebu cleanup 2023-01-14 19:19:34 -08:00
David Harris
b4dd7b21e6 generic cleanup 2023-01-14 19:02:38 -08:00
David Harris
fa61c9c4a5 generic cleanup 2023-01-14 18:56:46 -08:00
David Harris
21acb5e4e8 mmu cleanup 2023-01-14 18:27:53 -08:00
David Harris
894fdb8863 mmu cleanup 2023-01-14 18:20:47 -08:00
David Harris
316690c929 mmu cleanup 2023-01-14 18:14:38 -08:00
David Harris
00500c6685 mmu cleanup 2023-01-14 17:49:10 -08:00
David Harris
bba08c3202 mmu cleanup 2023-01-14 17:35:21 -08:00
David Harris
be029deb07 uncore cleanup 2023-01-14 17:21:07 -08:00
David Harris
16ff590a8c uncore cleanup 2023-01-14 17:09:11 -08:00
David Harris
b302f66baf uncore cleanup 2023-01-14 17:07:36 -08:00
David Harris
ae7e7b57ec uncore cleanup 2023-01-14 17:00:58 -08:00
David Harris
9ac905b5c0 sdc cleanup 2023-01-14 16:49:44 -08:00
David Harris
41c7d5c510 uncore cleanup 2023-01-14 06:15:35 -08:00
David Harris
da9f29b874 Wallypipeliendcore/soc cleanup 2023-01-14 05:57:50 -08:00
David Harris
50fae76207 csr & wally cleanup 2023-01-13 22:25:19 -08:00
David Harris
53d0d28828 csr cleanup 2023-01-13 22:12:06 -08:00
David Harris
b7f579a146 csr cleanup 2023-01-13 21:29:03 -08:00
David Harris
c5358da771 csr cleanup 2023-01-13 21:25:55 -08:00
David Harris
97bddf0d54 csr cleanup 2023-01-13 21:09:29 -08:00
David Harris
e4f4b31896 csr cleanup 2023-01-13 21:00:06 -08:00
David Harris
7358402bc0 csr cleanup 2023-01-13 20:55:21 -08:00
David Harris
9da2fae1f3 csr comments 2023-01-13 20:49:34 -08:00
David Harris
a9008cb293 trap comments 2023-01-13 19:50:44 -08:00
David Harris
370678f730 trap comments 2023-01-13 19:44:38 -08:00
David Harris
27f81b09ce privileged comments 2023-01-13 17:57:38 -08:00
Ross Thompson
77756e12eb Possible improvement to gshare. 2023-01-13 18:50:01 -06:00
Ross Thompson
4a73018d6e Merge branch 'rastemp' 2023-01-13 18:09:50 -06:00
Ross Thompson
17aebb8a3b Partial fix to RAS prediction accurracy. 2023-01-13 18:05:47 -06:00
Ross Thompson
53c8042276 Signal renames for ras. 2023-01-13 15:56:10 -06:00
Ross Thompson
8e3e8591a6 Removed 1 bit from instruction classification. 2023-01-13 15:19:53 -06:00
Ross Thompson
37481fce77 More branch predictor cleanup. 
Found small bug. The decode stage was using the predicted instruction class rather than the decoded instruction class.
 2023-01-13 12:57:18 -06:00
Ross Thompson
b26cec1ef4 Possible optimization of gshare. 
I don't believe the Writeback stage ghr is needed.
 2023-01-13 12:39:29 -06:00
Ross Thompson
f7dacb59f9 Possible minor enhancement to gshare. 2023-01-13 12:32:39 -06:00
Ross Thompson
36e74b7f4e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2023-01-13 10:26:07 -06:00
Ross Thompson
14ecaabbf6 Nearly complete RVVI tracer. 
Missing PMP registers and performance counters other than MCYCLE and MINSTRET.
 2023-01-12 18:43:39 -06:00
Ross Thompson
59b135d895 Added supervisor mode registers to tracer. 2023-01-12 17:04:41 -06:00
Ross Thompson
6500321aaf Added M CSRs to the CSRArray. 2023-01-12 16:51:51 -06:00
Ross Thompson
8981739310 added machine csr to logger. 2023-01-12 16:35:19 -06:00
Ross Thompson
f3443e2eca Added support to print the gprs. 2023-01-12 16:09:30 -06:00
Ross Thompson
0ea0e7a9e1 rvvi trace is coming alone nicely. 2023-01-12 14:46:31 -06:00
Ross Thompson
9a180f88f7 Completely stripped down imperas simulation. 
run with
vsim -c -do "do wally-pipelined-imperas.do rv64gc"
 2023-01-12 12:48:38 -06:00
Ross Thompson
5112ffcbc9 Stripped out all signature checking. 
Removed multiple tests loop.
Only runs 1 test now.
 2023-01-12 12:45:44 -06:00
Ross Thompson
8ee80c5d54 Created separate imperas testbench. 
Resolved logger issue with the duplicated instructions after commit.
 2023-01-12 12:07:07 -06:00
Ross Thompson
f59e1d03fc Added instruction logger. 2023-01-12 10:09:34 -06:00
David Harris
496d343660 Privileged unit formatting 2023-01-12 07:41:30 -08:00
David Harris
d586809903 restructured code for lint error related to CORRSHIFTSZ 2023-01-12 07:34:37 -08:00
David Harris
a3a736091c Restructured negateintres to avoid lint error, but one still shows on shiftcorrection 2023-01-12 07:28:52 -08:00
David Harris
b3e1badd31 MDU comment cleanup 2023-01-12 07:15:14 -08:00
David Harris
e67f125201 Header comments 2023-01-12 04:35:44 -08:00
Ross Thompson
b5250466ec Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2023-01-11 23:02:14 -06:00
Katherine Parry
4079f76a78 cleaned up all FPU files except for division 2023-01-11 22:02:30 -06:00
David Harris
49575dfb90 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-11 19:48:37 -08:00
David Harris
3aab0fae55 Removed unused wallypipelinedsocwrapper 2023-01-11 19:48:34 -08:00
Ross Thompson
3a41854f2b Completed review of LSU. 2023-01-11 19:06:03 -06:00
Ross Thompson
f15de26f5c Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-11 18:52:49 -06:00
Ross Thompson
2f3bf9eaf5 Improved LSU formating. 2023-01-11 18:52:46 -06:00
sarah-harris
3b363f5f9d privilege unit -> privileged unit in ifu.sv 
privilege unit -> privileged unit in ifu.sv
 2023-01-11 16:33:08 -08:00
Ross Thompson
0362e88098 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-11 17:26:11 -06:00
sarah-harris
829ab2c9aa Added Sarah.Harris@unlv.edu to alu.sv 
Added Sarah.Harris@unlv.edu to alu.sv
 2023-01-11 15:20:41 -08:00
Ross Thompson
a42d436962 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-11 17:15:49 -06:00
David Harris
7d93659f6b changed name to CORE-V-WALLY 2023-01-11 15:15:08 -08:00
Ross Thompson
a024dbccd6 Updated header for LSU. 2023-01-11 17:15:07 -06:00
David Harris
8f4b33c900 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-11 15:13:58 -08:00
Ross Thompson
96c61bd2ca Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-11 17:09:23 -06:00