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mmu cleanup
This commit is contained in:
David Harris
parent
894fdb8863
commit
21acb5e4e8
@ -29,39 +29,32 @@
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`include "wally-config.vh"
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module tlbcontrol #(parameter ITLB = 0) (
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// Current value of satp CSR (from privileged unit)
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input logic [`SVMODE_BITS-1:0] SATP_MODE,
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input logic [`XLEN-1:0] VAdr,
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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input logic [1:0] STATUS_MPP,
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input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor
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// 00 - TLB is not being accessed
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// 1x - TLB is accessed for a read (or an instruction)
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// x1 - TLB is accessed for a write
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// 11 - TLB is accessed for both read and write
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input logic ReadAccess, WriteAccess,
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input logic DisableTranslation,
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input logic TLBFlush, // Invalidate all TLB entries
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input logic [7:0] PTEAccessBits,
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input logic CAMHit,
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input logic Misaligned,
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output logic TLBMiss,
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output logic TLBHit,
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output logic TLBPageFault,
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output logic DAPageFault,
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output logic SV39Mode,
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output logic Translate
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input logic [`SVMODE_BITS-1:0] SATP_MODE,
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input logic [`XLEN-1:0] VAdr,
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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input logic [1:0] STATUS_MPP,
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input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor
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input logic ReadAccess, WriteAccess,
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input logic DisableTranslation,
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input logic TLBFlush, // Invalidate all TLB entries
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input logic [7:0] PTEAccessBits,
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input logic CAMHit,
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input logic Misaligned,
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output logic TLBMiss,
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output logic TLBHit,
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output logic TLBPageFault,
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output logic DAPageFault,
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output logic SV39Mode,
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output logic Translate
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);
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// Sections of the page table entry
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logic [1:0] EffectivePrivilegeMode;
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logic [1:0] EffectivePrivilegeMode;
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logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R, PTE_V; // Useful PTE Control Bits
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logic UpperBitsUnequalPageFault;
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logic TLBAccess;
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logic ImproperPrivilege;
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logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R, PTE_V; // Useful PTE Control Bits
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logic UpperBitsUnequalPageFault;
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logic TLBAccess;
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logic ImproperPrivilege;
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// Grab the sv mode from SATP and determine whether translation should occur
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assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1
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@ -70,8 +63,12 @@ module tlbcontrol #(parameter ITLB = 0) (
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// Determine whether TLB is being used
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assign TLBAccess = ReadAccess | WriteAccess;
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// Check whether upper bits of virtual addresss are all equal
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vm64check vm64check(.SATP_MODE, .VAdr, .SV39Mode, .UpperBitsUnequalPageFault);
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if (`XLEN==64) // Check whether upper bits of 64-bit virtual addressses are all equal
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vm64check vm64check(.SATP_MODE, .VAdr, .SV39Mode, .UpperBitsUnequalPageFault);
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else begin
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assign SV39Mode = 0;
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assign UpperBitsUnequalPageFault = 0;
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end
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// unswizzle useful PTE bits
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assign {PTE_D, PTE_A} = PTEAccessBits[7:6];
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@ -28,18 +28,18 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module tlblru #(parameter TLB_ENTRIES = 8) (
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input logic clk, reset,
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input logic TLBWrite,
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input logic TLBFlush,
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input logic [TLB_ENTRIES-1:0] Matches,
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input logic CAMHit,
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output logic [TLB_ENTRIES-1:0] WriteEnables
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input logic clk, reset,
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input logic TLBWrite,
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input logic TLBFlush,
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input logic [TLB_ENTRIES-1:0] Matches,
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input logic CAMHit,
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output logic [TLB_ENTRIES-1:0] WriteEnables
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);
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logic [TLB_ENTRIES-1:0] RUBits, RUBitsNext, RUBitsAccessed;
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logic [TLB_ENTRIES-1:0] WriteLines;
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logic [TLB_ENTRIES-1:0] AccessLines; // One-hot encodings of which line is being accessed
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logic AllUsed; // High if the next access causes all RU bits to be 1
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logic [TLB_ENTRIES-1:0] RUBits, RUBitsNext, RUBitsAccessed;
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logic [TLB_ENTRIES-1:0] WriteLines;
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logic [TLB_ENTRIES-1:0] AccessLines; // One-hot encodings of which line is being accessed
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logic AllUsed; // High if the next access causes all RU bits to be 1
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// Find the first line not recently used
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priorityonehot #(TLB_ENTRIES) nru(.a(~RUBits), .y(WriteLines));
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@ -29,20 +29,18 @@
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`include "wally-config.vh"
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module vm64check (
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input logic [`SVMODE_BITS-1:0] SATP_MODE,
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input logic [`XLEN-1:0] VAdr,
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output logic SV39Mode, UpperBitsUnequalPageFault
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input logic [`SVMODE_BITS-1:0] SATP_MODE,
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input logic [`XLEN-1:0] VAdr,
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output logic SV39Mode,
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output logic UpperBitsUnequalPageFault
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);
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if (`XLEN==64) begin:rv64
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assign SV39Mode = (SATP_MODE == `SV39);
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// page fault if upper bits aren't all the same
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logic UpperEqual39, UpperEqual48;
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assign UpperEqual39 = &(VAdr[63:38]) | ~|(VAdr[63:38]);
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assign UpperEqual48 = &(VAdr[63:47]) | ~|(VAdr[63:47]);
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assign UpperBitsUnequalPageFault = SV39Mode ? ~UpperEqual39 : ~UpperEqual48;
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end else begin
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assign SV39Mode = 0;
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assign UpperBitsUnequalPageFault = 0;
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end
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logic eq_63_47, eq_46_38;
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assign SV39Mode = (SATP_MODE == `SV39);
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// page fault if upper bits aren't all the same
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assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]);
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assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]);
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assign UpperBitsUnequalPageFault = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47;
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endmodule
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