mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-02 01:44:41 +00:00
cache cleanup
This commit is contained in:
David Harris
parent
94d01d292e
commit
364cf97c34
27
pipelined/src/cache/cacheLRU.sv
vendored
27
pipelined/src/cache/cacheLRU.sv
vendored
@ -27,22 +27,27 @@
|
||||
`include "wally-config.vh"
|
||||
|
||||
module cacheLRU
|
||||
#(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128)(
|
||||
input logic clk, reset, CacheEn, FlushStage,
|
||||
input logic [NUMWAYS-1:0] HitWay,
|
||||
input logic [NUMWAYS-1:0] ValidWay,
|
||||
output logic [NUMWAYS-1:0] VictimWay,
|
||||
input logic [SETLEN-1:0] CAdr,
|
||||
input logic [SETLEN-1:0] PAdr,
|
||||
input logic LRUWriteEn, SetValid, InvalidateCache, FlushCache);
|
||||
#(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128) (
|
||||
input logic clk, reset,
|
||||
input logic CacheEn,
|
||||
input logic FlushStage,
|
||||
input logic [NUMWAYS-1:0] HitWay,
|
||||
input logic [NUMWAYS-1:0] ValidWay,
|
||||
input logic [SETLEN-1:0] CAdr,
|
||||
input logic [SETLEN-1:0] PAdr,
|
||||
input logic LRUWriteEn,
|
||||
input logic SetValid,
|
||||
input logic InvalidateCache,
|
||||
input logic FlushCache,
|
||||
output logic [NUMWAYS-1:0] VictimWay
|
||||
);
|
||||
|
||||
localparam LOGNUMWAYS = $clog2(NUMWAYS);
|
||||
|
||||
logic [NUMWAYS-2:0] LRUMemory [NUMLINES-1:0];
|
||||
logic [NUMWAYS-2:0] CurrLRU;
|
||||
logic [NUMWAYS-2:0] NextLRU;
|
||||
logic [NUMWAYS-1:0] Way;
|
||||
|
||||
localparam LOGNUMWAYS = $clog2(NUMWAYS);
|
||||
|
||||
logic [LOGNUMWAYS-1:0] WayEncoded;
|
||||
logic [NUMWAYS-2:0] WayExpanded;
|
||||
logic AllValid;
|
||||
|
||||
123
pipelined/src/cache/cachefsm.sv
vendored
123
pipelined/src/cache/cachefsm.sv
vendored
@ -26,48 +26,49 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module cachefsm
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
// inputs from IEU
|
||||
input logic FlushStage,
|
||||
input logic [1:0] CacheRW,
|
||||
input logic [1:0] CacheAtomic,
|
||||
input logic FlushCache,
|
||||
input logic InvalidateCache,
|
||||
// hazard inputs
|
||||
input logic Stall,
|
||||
// Bus inputs
|
||||
input logic CacheBusAck,
|
||||
// dcache internals
|
||||
input logic CacheHit,
|
||||
input logic LineDirty,
|
||||
input logic FlushAdrFlag,
|
||||
input logic FlushWayFlag,
|
||||
|
||||
// hazard outputs
|
||||
output logic CacheStall,
|
||||
// counter outputs
|
||||
output logic CacheMiss,
|
||||
output logic CacheAccess,
|
||||
// Bus outputs
|
||||
output logic CacheCommitted,
|
||||
output logic [1:0] CacheBusRW,
|
||||
module cachefsm (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
// inputs from IEU
|
||||
input logic FlushStage,
|
||||
input logic [1:0] CacheRW,
|
||||
input logic [1:0] CacheAtomic,
|
||||
input logic FlushCache,
|
||||
input logic InvalidateCache,
|
||||
// hazard inputs
|
||||
input logic Stall,
|
||||
// Bus inputs
|
||||
input logic CacheBusAck,
|
||||
// dcache internals
|
||||
input logic CacheHit,
|
||||
input logic LineDirty,
|
||||
input logic FlushAdrFlag,
|
||||
input logic FlushWayFlag,
|
||||
|
||||
// dcache internals
|
||||
output logic SelAdr,
|
||||
output logic ClearValid,
|
||||
output logic ClearDirty,
|
||||
output logic SetDirty,
|
||||
output logic SetValid,
|
||||
output logic SelWriteback,
|
||||
output logic LRUWriteEn,
|
||||
output logic SelFlush,
|
||||
output logic FlushAdrCntEn,
|
||||
output logic FlushWayCntEn,
|
||||
output logic FlushCntRst,
|
||||
output logic SelFetchBuffer,
|
||||
output logic CacheEn);
|
||||
// hazard outputs
|
||||
output logic CacheStall,
|
||||
// counter outputs
|
||||
output logic CacheMiss,
|
||||
output logic CacheAccess,
|
||||
// Bus outputs
|
||||
output logic CacheCommitted,
|
||||
output logic [1:0] CacheBusRW,
|
||||
|
||||
// dcache internals
|
||||
output logic SelAdr,
|
||||
output logic ClearValid,
|
||||
output logic ClearDirty,
|
||||
output logic SetDirty,
|
||||
output logic SetValid,
|
||||
output logic SelWriteback,
|
||||
output logic LRUWriteEn,
|
||||
output logic SelFlush,
|
||||
output logic FlushAdrCntEn,
|
||||
output logic FlushWayCntEn,
|
||||
output logic FlushCntRst,
|
||||
output logic SelFetchBuffer,
|
||||
output logic CacheEn
|
||||
);
|
||||
|
||||
logic resetDelay;
|
||||
logic AMO, StoreAMO;
|
||||
@ -75,7 +76,7 @@ module cachefsm
|
||||
logic AnyMiss;
|
||||
logic FlushFlag;
|
||||
|
||||
typedef enum logic [3:0] {STATE_READY, // hit states
|
||||
typedef enum logic [3:0]{STATE_READY, // hit states
|
||||
// miss states
|
||||
STATE_FETCH,
|
||||
STATE_WRITEBACK,
|
||||
@ -111,28 +112,28 @@ module cachefsm
|
||||
always_comb begin
|
||||
NextState = STATE_READY;
|
||||
case (CurrState)
|
||||
STATE_READY: if(InvalidateCache) NextState = STATE_READY;
|
||||
else if(FlushCache) NextState = STATE_FLUSH;
|
||||
STATE_READY: if(InvalidateCache) NextState = STATE_READY;
|
||||
else if(FlushCache) NextState = STATE_FLUSH;
|
||||
// Delayed LRU update. Cannot check if victim line is dirty on this cycle.
|
||||
// To optimize do the fetch first, then eviction if necessary.
|
||||
else if(AnyMiss & ~LineDirty) NextState = STATE_FETCH;
|
||||
else if(AnyMiss & LineDirty) NextState = STATE_WRITEBACK;
|
||||
else NextState = STATE_READY;
|
||||
STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE;
|
||||
else NextState = STATE_FETCH;
|
||||
STATE_WRITE_LINE: NextState = STATE_READ_HOLD;
|
||||
STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD;
|
||||
else NextState = STATE_READY;
|
||||
STATE_WRITEBACK: if(CacheBusAck) NextState = STATE_FETCH;
|
||||
else NextState = STATE_WRITEBACK;
|
||||
else if(AnyMiss & ~LineDirty) NextState = STATE_FETCH;
|
||||
else if(AnyMiss & LineDirty) NextState = STATE_WRITEBACK;
|
||||
else NextState = STATE_READY;
|
||||
STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE;
|
||||
else NextState = STATE_FETCH;
|
||||
STATE_WRITE_LINE: NextState = STATE_READ_HOLD;
|
||||
STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD;
|
||||
else NextState = STATE_READY;
|
||||
STATE_WRITEBACK: if(CacheBusAck) NextState = STATE_FETCH;
|
||||
else NextState = STATE_WRITEBACK;
|
||||
// eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
|
||||
STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITEBACK;
|
||||
else if (FlushFlag) NextState = STATE_READ_HOLD;
|
||||
else NextState = STATE_FLUSH;
|
||||
STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH;
|
||||
else if(CacheBusAck) NextState = STATE_READ_HOLD;
|
||||
else NextState = STATE_FLUSH_WRITEBACK;
|
||||
default: NextState = STATE_READY;
|
||||
STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITEBACK;
|
||||
else if (FlushFlag) NextState = STATE_READ_HOLD;
|
||||
else NextState = STATE_FLUSH;
|
||||
STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH;
|
||||
else if(CacheBusAck) NextState = STATE_READ_HOLD;
|
||||
else NextState = STATE_FLUSH_WRITEBACK;
|
||||
default: NextState = STATE_READY;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
92
pipelined/src/cache/cacheway.sv
vendored
92
pipelined/src/cache/cacheway.sv
vendored
@ -26,56 +26,54 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
|
||||
parameter OFFSETLEN = 5, parameter INDEXLEN = 9, parameter DIRTY_BITS = 1) (
|
||||
input logic clk,
|
||||
input logic CacheEn,
|
||||
input logic reset,
|
||||
input logic [$clog2(NUMLINES)-1:0] CAdr,
|
||||
input logic [`PA_BITS-1:0] PAdr,
|
||||
input logic [LINELEN-1:0] LineWriteData,
|
||||
input logic SetValid,
|
||||
input logic ClearValid,
|
||||
input logic SetDirty,
|
||||
input logic ClearDirty,
|
||||
input logic SelWriteback,
|
||||
input logic SelFlush,
|
||||
input logic VictimWay,
|
||||
input logic FlushWay,
|
||||
input logic InvalidateCache,
|
||||
input logic FlushStage,
|
||||
// input logic [(`XLEN-1)/8:0] ByteMask,
|
||||
input logic [LINELEN/8-1:0] LineByteMask,
|
||||
module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
|
||||
OFFSETLEN = 5, INDEXLEN = 9, DIRTY_BITS = 1) (
|
||||
input logic clk,
|
||||
input logic CacheEn,
|
||||
input logic reset,
|
||||
input logic [$clog2(NUMLINES)-1:0] CAdr,
|
||||
input logic [`PA_BITS-1:0] PAdr,
|
||||
input logic [LINELEN-1:0] LineWriteData,
|
||||
input logic SetValid,
|
||||
input logic ClearValid,
|
||||
input logic SetDirty,
|
||||
input logic ClearDirty,
|
||||
input logic SelWriteback,
|
||||
input logic SelFlush,
|
||||
input logic VictimWay,
|
||||
input logic FlushWay,
|
||||
input logic InvalidateCache,
|
||||
input logic FlushStage,
|
||||
input logic [LINELEN/8-1:0] LineByteMask,
|
||||
|
||||
output logic [LINELEN-1:0] ReadDataLineWay,
|
||||
output logic HitWay,
|
||||
output logic ValidWay,
|
||||
output logic DirtyWay,
|
||||
output logic [TAGLEN-1:0] TagWay);
|
||||
output logic [LINELEN-1:0] ReadDataLineWay,
|
||||
output logic HitWay,
|
||||
output logic ValidWay,
|
||||
output logic DirtyWay,
|
||||
output logic [TAGLEN-1:0] TagWay);
|
||||
|
||||
localparam integer WORDSPERLINE = LINELEN/`XLEN;
|
||||
localparam integer BYTESPERLINE = LINELEN/8;
|
||||
localparam LOGWPL = $clog2(WORDSPERLINE);
|
||||
localparam LOGXLENBYTES = $clog2(`XLEN/8);
|
||||
localparam integer BYTESPERWORD = `XLEN/8;
|
||||
localparam integer WORDSPERLINE = LINELEN/`XLEN;
|
||||
localparam integer BYTESPERLINE = LINELEN/8;
|
||||
localparam LOGWPL = $clog2(WORDSPERLINE);
|
||||
localparam LOGXLENBYTES = $clog2(`XLEN/8);
|
||||
localparam integer BYTESPERWORD = `XLEN/8;
|
||||
|
||||
logic [NUMLINES-1:0] ValidBits;
|
||||
logic [NUMLINES-1:0] DirtyBits;
|
||||
logic [LINELEN-1:0] ReadDataLine;
|
||||
logic [TAGLEN-1:0] ReadTag;
|
||||
logic Dirty;
|
||||
logic SelTag;
|
||||
logic SelectedWriteWordEn;
|
||||
logic [LINELEN/8-1:0] FinalByteMask;
|
||||
logic SetValidEN;
|
||||
logic SetValidWay;
|
||||
logic ClearValidWay;
|
||||
logic SetDirtyWay;
|
||||
logic ClearDirtyWay;
|
||||
logic SelNonHit;
|
||||
logic SelData;
|
||||
logic FlushWayEn, VictimWayEn;
|
||||
|
||||
logic [NUMLINES-1:0] ValidBits;
|
||||
logic [NUMLINES-1:0] DirtyBits;
|
||||
logic [LINELEN-1:0] ReadDataLine;
|
||||
logic [TAGLEN-1:0] ReadTag;
|
||||
logic Dirty;
|
||||
logic SelTag;
|
||||
logic SelectedWriteWordEn;
|
||||
logic [LINELEN/8-1:0] FinalByteMask;
|
||||
logic SetValidEN;
|
||||
logic SetValidWay;
|
||||
logic ClearValidWay;
|
||||
logic SetDirtyWay;
|
||||
logic ClearDirtyWay;
|
||||
logic SelNonHit;
|
||||
logic SelData;
|
||||
logic FlushWayEn, VictimWayEn;
|
||||
|
||||
// FlushWay and VictimWay are part of a one hot way selection. Must clear them if FlushWay not selected
|
||||
// or VictimWay not selected.
|
||||
|
||||
21
pipelined/src/cache/subcachelineread.sv
vendored
21
pipelined/src/cache/subcachelineread.sv
vendored
@ -27,26 +27,27 @@
|
||||
`include "wally-config.vh"
|
||||
|
||||
module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL)(
|
||||
input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr,
|
||||
input logic [LINELEN-1:0] ReadDataLine,
|
||||
output logic [WORDLEN-1:0] ReadDataWord);
|
||||
input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr,
|
||||
input logic [LINELEN-1:0] ReadDataLine,
|
||||
output logic [WORDLEN-1:0] ReadDataWord
|
||||
);
|
||||
|
||||
localparam WORDSPERLINE = LINELEN/MUXINTERVAL;
|
||||
// pad is for icache. Muxing extends over the cacheline boundary.
|
||||
localparam PADLEN = WORDLEN-MUXINTERVAL;
|
||||
logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0] ReadDataLinePad;
|
||||
logic [WORDLEN-1:0] ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0];
|
||||
|
||||
// pad is for icache. Muxing extends over the cacheline boundary.
|
||||
logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0] ReadDataLinePad;
|
||||
logic [WORDLEN-1:0] ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0];
|
||||
|
||||
if (PADLEN > 0) begin
|
||||
logic [PADLEN-1:0] Pad;
|
||||
assign Pad = '0;
|
||||
assign ReadDataLinePad = {Pad, ReadDataLine};
|
||||
assign ReadDataLinePad = {{PADLEN{1'b0}}, ReadDataLine};
|
||||
end else assign ReadDataLinePad = ReadDataLine;
|
||||
|
||||
genvar index;
|
||||
for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux
|
||||
assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1: (index*MUXINTERVAL)];
|
||||
assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1 : (index*MUXINTERVAL)];
|
||||
end
|
||||
|
||||
// variable input mux
|
||||
assign ReadDataWord = ReadDataLineSets[PAdr];
|
||||
endmodule
|
||||
|
||||
Loading…
Reference in New Issue
Block a user