pipelined/src/ieu/ieu.sv

This commit is contained in:
David Harris 2023-01-17 06:08:26 -08:00
parent 3124ebc3e1
commit 2c00ac5254

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@ -65,7 +65,7 @@ module ieu (
input logic StallD, StallE, StallM, StallW, // Final stall signals ***
input logic FlushD, FlushE, FlushM, FlushW, // Flush signals
output logic FCvtIntStallD, LoadStallD, // Intermediate stall signals ***
output logic MDUStallD, CSRRdStallD, StoreStallD
output logic MDUStallD, CSRRdStallD, StoreStallD,
output logic PCSrcE, // Select next PC (between PC+4 and IEUAdrE)
output logic CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction ***
output logic CSRWriteFenceM // CSR write is a fence instruction ***