mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-02 09:45:18 +00:00
csr & wally cleanup
This commit is contained in:
David Harris
parent
53d0d28828
commit
50fae76207
@ -28,140 +28,140 @@
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/* verilator lint_on UNUSED */
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module wallypipelinedcore (
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input logic clk, reset,
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input logic clk, reset,
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// Privileged
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input logic MTimerInt, MExtInt, SExtInt, MSwInt,
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input logic [63:0] MTIME_CLINT,
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input logic MTimerInt, MExtInt, SExtInt, MSwInt,
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input logic [63:0] MTIME_CLINT,
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// Bus Interface
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input logic [`AHBW-1:0] HRDATA,
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input logic HREADY, HRESP,
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output logic HCLK, HRESETn,
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output logic [`PA_BITS-1:0] HADDR,
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output logic [`AHBW-1:0] HWDATA,
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output logic [`XLEN/8-1:0] HWSTRB,
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output logic HWRITE,
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output logic [2:0] HSIZE,
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output logic [2:0] HBURST,
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output logic [3:0] HPROT,
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output logic [1:0] HTRANS,
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output logic HMASTLOCK
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input logic [`AHBW-1:0] HRDATA,
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input logic HREADY, HRESP,
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output logic HCLK, HRESETn,
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output logic [`PA_BITS-1:0] HADDR,
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output logic [`AHBW-1:0] HWDATA,
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output logic [`XLEN/8-1:0] HWSTRB,
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output logic HWRITE,
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output logic [2:0] HSIZE,
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output logic [2:0] HBURST,
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output logic [3:0] HPROT,
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output logic [1:0] HTRANS,
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output logic HMASTLOCK
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);
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logic StallF, StallD, StallE, StallM, StallW;
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logic FlushD, FlushE, FlushM, FlushW;
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logic RetM;
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logic StallF, StallD, StallE, StallM, StallW;
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logic FlushD, FlushE, FlushM, FlushW;
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logic RetM;
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(* mark_debug = "true" *) logic TrapM;
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// new signals that must connect through DP
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logic IntDivE, W64E;
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logic CSRReadM, CSRWriteM, PrivilegedM;
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logic [1:0] AtomicM;
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logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; //, SrcAE, SrcBE;
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// signals that must connect through DP
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logic IntDivE, W64E;
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logic CSRReadM, CSRWriteM, PrivilegedM;
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logic [1:0] AtomicM;
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logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE;
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(* mark_debug = "true" *) logic [`XLEN-1:0] SrcAM;
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logic [2:0] Funct3E;
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logic [31:0] InstrD;
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logic [2:0] Funct3E;
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logic [31:0] InstrD;
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(* mark_debug = "true" *) logic [31:0] InstrM;
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logic [`XLEN-1:0] PCF, PCE, PCLinkE;
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logic [`XLEN-1:0] PCF, PCE, PCLinkE;
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(* mark_debug = "true" *) logic [`XLEN-1:0] PCM;
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logic [`XLEN-1:0] CSRReadValW, MDUResultW;
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logic [`XLEN-1:0] UnalignedPCNextF, PCNext2F;
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logic [`XLEN-1:0] CSRReadValW, MDUResultW;
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logic [`XLEN-1:0] UnalignedPCNextF, PCNext2F;
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(* mark_debug = "true" *) logic [1:0] MemRWM;
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(* mark_debug = "true" *) logic InstrValidM;
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logic InstrMisalignedFaultM;
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logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
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logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM;
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logic LoadMisalignedFaultM, LoadAccessFaultM;
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logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM;
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logic InvalidateICacheM, FlushDCacheM;
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logic PCSrcE;
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logic CSRWriteFenceM;
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logic DivBusyE;
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logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD;
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logic SquashSCW;
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logic InstrMisalignedFaultM;
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logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
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logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM;
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logic LoadMisalignedFaultM, LoadAccessFaultM;
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logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM;
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logic InvalidateICacheM, FlushDCacheM;
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logic PCSrcE;
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logic CSRWriteFenceM;
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logic DivBusyE;
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logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD;
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logic SquashSCW;
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// floating point unit signals
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logic [2:0] FRM_REGW;
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logic [4:0] RdE, RdM, RdW;
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logic FPUStallD;
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logic FWriteIntE;
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logic [`FLEN-1:0] FWriteDataM;
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logic [`XLEN-1:0] FIntResM;
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logic [`XLEN-1:0] FCvtIntResW;
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logic FCvtIntW;
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logic FDivBusyE;
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logic IllegalFPUInstrM;
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logic FRegWriteM;
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logic FCvtIntStallD;
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logic FpLoadStoreM;
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logic [4:0] SetFflagsM;
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logic [`XLEN-1:0] FIntDivResultW;
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logic [2:0] FRM_REGW;
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logic [4:0] RdE, RdM, RdW;
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logic FPUStallD;
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logic FWriteIntE;
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logic [`FLEN-1:0] FWriteDataM;
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logic [`XLEN-1:0] FIntResM;
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logic [`XLEN-1:0] FCvtIntResW;
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logic FCvtIntW;
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logic FDivBusyE;
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logic IllegalFPUInstrM;
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logic FRegWriteM;
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logic FCvtIntStallD;
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logic FpLoadStoreM;
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logic [4:0] SetFflagsM;
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logic [`XLEN-1:0] FIntDivResultW;
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// memory management unit signals
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logic ITLBWriteF;
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logic ITLBMissF;
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logic [`XLEN-1:0] SATP_REGW;
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logic STATUS_MXR, STATUS_SUM, STATUS_MPRV;
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logic [1:0] STATUS_MPP, STATUS_FS;
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logic [1:0] PrivilegeModeW;
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logic [`XLEN-1:0] PTE;
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logic [1:0] PageType;
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logic sfencevmaM, WFIStallM;
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logic SelHPTW;
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logic ITLBWriteF;
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logic ITLBMissF;
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logic [`XLEN-1:0] SATP_REGW;
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logic STATUS_MXR, STATUS_SUM, STATUS_MPRV;
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logic [1:0] STATUS_MPP, STATUS_FS;
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logic [1:0] PrivilegeModeW;
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logic [`XLEN-1:0] PTE;
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logic [1:0] PageType;
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logic sfencevmaM, WFIStallM;
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logic SelHPTW;
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// PMA checker signals
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var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0];
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var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0];
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var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0];
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var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0];
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// IMem stalls
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logic IFUStallF;
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logic LSUStallM;
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logic IFUStallF;
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logic LSUStallM;
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// cpu lsu interface
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logic [2:0] Funct3M;
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logic [`XLEN-1:0] IEUAdrE;
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logic [2:0] Funct3M;
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logic [`XLEN-1:0] IEUAdrE;
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(* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] IEUAdrM;
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logic [`LLEN-1:0] ReadDataW;
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logic CommittedM;
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logic [`LLEN-1:0] ReadDataW;
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logic CommittedM;
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// AHB ifu interface
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logic [`PA_BITS-1:0] IFUHADDR;
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logic [2:0] IFUHBURST;
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logic [1:0] IFUHTRANS;
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logic [2:0] IFUHSIZE;
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logic IFUHWRITE;
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logic IFUHREADY;
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logic [`PA_BITS-1:0] IFUHADDR;
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logic [2:0] IFUHBURST;
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logic [1:0] IFUHTRANS;
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logic [2:0] IFUHSIZE;
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logic IFUHWRITE;
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logic IFUHREADY;
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// AHB LSU interface
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logic [`PA_BITS-1:0] LSUHADDR;
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logic [`XLEN-1:0] LSUHWDATA;
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logic [`XLEN/8-1:0] LSUHWSTRB;
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logic LSUHWRITE;
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logic LSUHREADY;
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logic [`PA_BITS-1:0] LSUHADDR;
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logic [`XLEN-1:0] LSUHWDATA;
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logic [`XLEN/8-1:0] LSUHWSTRB;
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logic LSUHWRITE;
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logic LSUHREADY;
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logic BPPredWrongE;
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logic DirPredictionWrongM;
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logic BTBPredPCWrongM;
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logic RASPredPCWrongM;
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logic PredictionInstrClassWrongM;
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logic [3:0] InstrClassM;
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logic InstrAccessFaultF, HPTWInstrAccessFaultM;
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logic [2:0] LSUHSIZE;
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logic [2:0] LSUHBURST;
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logic [1:0] LSUHTRANS;
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logic BPPredWrongE;
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logic DirPredictionWrongM;
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logic BTBPredPCWrongM;
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logic RASPredPCWrongM;
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logic PredictionInstrClassWrongM;
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logic [3:0] InstrClassM;
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logic InstrAccessFaultF, HPTWInstrAccessFaultM;
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logic [2:0] LSUHSIZE;
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logic [2:0] LSUHBURST;
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logic [1:0] LSUHTRANS;
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logic DCacheMiss;
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logic DCacheAccess;
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logic ICacheMiss;
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logic ICacheAccess;
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logic BreakpointFaultM, EcallFaultM;
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logic InstrDAPageFaultF;
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logic BigEndianM;
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logic FCvtIntE;
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logic CommittedF;
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logic DCacheMiss;
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logic DCacheAccess;
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logic ICacheMiss;
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logic ICacheAccess;
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logic BreakpointFaultM, EcallFaultM;
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logic InstrDAPageFaultF;
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logic BigEndianM;
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logic FCvtIntE;
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logic CommittedF;
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// instruction fetch unit: PC, branch prediction, instruction cache
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ifu ifu(
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.clk, .reset,
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.StallF, .StallD, .StallE, .StallM, .StallW,
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@ -197,10 +197,9 @@ module wallypipelinedcore (
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// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.InstrAccessFaultF,
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.InstrDAPageFaultF
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); // instruction fetch unit: PC, branch prediction, instruction cache
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.InstrDAPageFaultF);
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// integer execution unit: integer register file, datapath and controller
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ieu ieu(
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.clk, .reset,
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@ -235,27 +234,25 @@ module wallypipelinedcore (
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.FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD,
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.PCSrcE,
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.CSRReadM, .CSRWriteM, .PrivilegedM,
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.CSRWriteFenceM, .StoreStallD
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); // integer execution unit: integer register file, datapath and controller
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.CSRWriteFenceM, .StoreStallD);
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lsu lsu(
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.clk, .reset, .StallM, .FlushM, .StallW,
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.FlushW,
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// CPU interface
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.MemRWM, .Funct3M, .Funct7M(InstrM[31:25]),
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.AtomicM,
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.CommittedM, .DCacheMiss, .DCacheAccess,
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.SquashSCW,
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.FpLoadStoreM,
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.FWriteDataM,
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//.DataMisalignedM(DataMisalignedM),
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.IEUAdrE, .IEUAdrM, .WriteDataM,
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.ReadDataW, .FlushDCacheM,
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// connected to ahb (all stay the same)
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.LSUHADDR,
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.HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, .LSUHBURST, .LSUHTRANS,
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.LSUHWRITE, .LSUHREADY,
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.clk, .reset, .StallM, .FlushM, .StallW,
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.FlushW,
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// CPU interface
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.MemRWM, .Funct3M, .Funct7M(InstrM[31:25]),
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.AtomicM,
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.CommittedM, .DCacheMiss, .DCacheAccess,
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.SquashSCW,
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.FpLoadStoreM,
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.FWriteDataM,
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//.DataMisalignedM(DataMisalignedM),
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.IEUAdrE, .IEUAdrM, .WriteDataM,
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.ReadDataW, .FlushDCacheM,
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// connected to ahb (all stay the same)
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.LSUHADDR,
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.HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, .LSUHBURST, .LSUHTRANS,
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.LSUHWRITE, .LSUHREADY,
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// connect to csr or privilege and stay the same.
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.PrivilegeModeW, .BigEndianM, // connects to csr
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@ -279,139 +276,131 @@ module wallypipelinedcore (
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.InstrDAPageFaultF,
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.PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
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.LSUStallM); // change to LSUStallM
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// *** Ross: please make EBU conditional when only supporting internal memories
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.LSUStallM);
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if(`BUS) begin : ebu
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ebu ebu(// IFU connections
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.clk, .reset,
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// IFU interface
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.IFUHADDR,
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.IFUHBURST,
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.IFUHTRANS,
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.IFUHREADY,
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.IFUHSIZE,
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// LSU interface
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.LSUHADDR,
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.LSUHWDATA,
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.LSUHWSTRB,
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.LSUHSIZE,
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.LSUHBURST,
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.LSUHTRANS,
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.LSUHWRITE,
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.LSUHREADY,
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// BUS interface
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.HREADY, .HRESP, .HCLK, .HRESETn,
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.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
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.HPROT, .HTRANS, .HMASTLOCK);
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.clk, .reset,
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// IFU interface
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.IFUHADDR,
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.IFUHBURST,
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.IFUHTRANS,
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.IFUHREADY,
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.IFUHSIZE,
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// LSU interface
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.LSUHADDR,
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.LSUHWDATA,
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.LSUHWSTRB,
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.LSUHSIZE,
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.LSUHBURST,
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.LSUHTRANS,
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.LSUHWRITE,
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.LSUHREADY,
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// BUS interface
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.HREADY, .HRESP, .HCLK, .HRESETn,
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.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
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.HPROT, .HTRANS, .HMASTLOCK);
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end
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hazard hzu(
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.BPPredWrongE, .CSRWriteFenceM, .RetM, .TrapM,
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.LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD,
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.LSUStallM, .IFUStallF,
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.FCvtIntStallD, .FPUStallD,
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// global stall and flush control
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hazard hzu(
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.BPPredWrongE, .CSRWriteFenceM, .RetM, .TrapM,
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.LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD,
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.LSUStallM, .IFUStallF,
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.FCvtIntStallD, .FPUStallD,
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.DivBusyE, .FDivBusyE,
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.EcallFaultM, .BreakpointFaultM,
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.WFIStallM,
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// Stall & flush outputs
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.WFIStallM,
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// Stall & flush outputs
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.StallF, .StallD, .StallE, .StallM, .StallW,
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.FlushD, .FlushE, .FlushM, .FlushW
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); // global stall and flush control
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.FlushD, .FlushE, .FlushM, .FlushW);
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if (`ZICSR_SUPPORTED) begin:priv
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privileged priv(
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.clk, .reset,
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.FlushD, .FlushE, .FlushM, .FlushW,
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.StallD, .StallE, .StallM, .StallW,
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.CSRReadM, .CSRWriteM, .SrcAM, .PCM, .PCNext2F,
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.InstrM, .CSRReadValW, .UnalignedPCNextF,
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.RetM, .TrapM,
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.sfencevmaM,
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.InstrValidM, .CommittedM, .CommittedF,
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.FRegWriteM, .LoadStallD,
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.DirPredictionWrongM, .BTBPredPCWrongM,
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.RASPredPCWrongM, .PredictionInstrClassWrongM,
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.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
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.InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
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.InstrMisalignedFaultM, .IllegalIEUInstrFaultD,
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.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
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.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
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.MTIME_CLINT,
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.IEUAdrM,
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.SetFflagsM,
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// Trap signals from pmp/pma in mmu
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// *** do these need to be split up into one for dmem and one for ifu?
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// instead, could we only care about the instr and F pins that come from ifu and only care about the load/store and m pins that come from dmem?
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.InstrAccessFaultF, .HPTWInstrAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW,
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.IllegalFPUInstrM,
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.PrivilegeModeW, .SATP_REGW,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS,
|
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
|
||||
.FRM_REGW,.BreakpointFaultM, .EcallFaultM, .WFIStallM, .BigEndianM
|
||||
);
|
||||
end else begin
|
||||
assign CSRReadValW = 0;
|
||||
assign UnalignedPCNextF = PCNext2F;
|
||||
assign RetM = 0;
|
||||
assign TrapM = 0;
|
||||
assign WFIStallM = 0;
|
||||
assign sfencevmaM = 0;
|
||||
assign BigEndianM = 0;
|
||||
end
|
||||
if (`M_SUPPORTED) begin:mdu
|
||||
mdu mdu(
|
||||
.clk, .reset,
|
||||
.ForwardedSrcAE, .ForwardedSrcBE,
|
||||
.Funct3E, .Funct3M, .IntDivE, .W64E,
|
||||
.MDUResultW, .DivBusyE,
|
||||
.StallM, .StallW, .FlushE, .FlushM, .FlushW
|
||||
);
|
||||
end else begin // no M instructions supported
|
||||
assign MDUResultW = 0;
|
||||
assign DivBusyE = 0;
|
||||
end
|
||||
// privileged unit
|
||||
if (`ZICSR_SUPPORTED) begin:priv
|
||||
privileged priv(
|
||||
.clk, .reset,
|
||||
.FlushD, .FlushE, .FlushM, .FlushW,
|
||||
.StallD, .StallE, .StallM, .StallW,
|
||||
.CSRReadM, .CSRWriteM, .SrcAM, .PCM, .PCNext2F,
|
||||
.InstrM, .CSRReadValW, .UnalignedPCNextF,
|
||||
.RetM, .TrapM,
|
||||
.sfencevmaM,
|
||||
.InstrValidM, .CommittedM, .CommittedF,
|
||||
.FRegWriteM, .LoadStallD,
|
||||
.DirPredictionWrongM, .BTBPredPCWrongM,
|
||||
.RASPredPCWrongM, .PredictionInstrClassWrongM,
|
||||
.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
|
||||
.InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
|
||||
.InstrMisalignedFaultM, .IllegalIEUInstrFaultD,
|
||||
.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
|
||||
.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
|
||||
.MTIME_CLINT,
|
||||
.IEUAdrM,
|
||||
.SetFflagsM,
|
||||
.InstrAccessFaultF, .HPTWInstrAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW,
|
||||
.IllegalFPUInstrM,
|
||||
.PrivilegeModeW, .SATP_REGW,
|
||||
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS,
|
||||
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
|
||||
.FRM_REGW,.BreakpointFaultM, .EcallFaultM, .WFIStallM, .BigEndianM);
|
||||
end else begin
|
||||
assign CSRReadValW = 0;
|
||||
assign UnalignedPCNextF = PCNext2F;
|
||||
assign RetM = 0;
|
||||
assign TrapM = 0;
|
||||
assign WFIStallM = 0;
|
||||
assign sfencevmaM = 0;
|
||||
assign BigEndianM = 0;
|
||||
end
|
||||
|
||||
if (`F_SUPPORTED) begin:fpu
|
||||
fpu fpu(
|
||||
.clk, .reset,
|
||||
.FRM_REGW, // Rounding mode from CSR
|
||||
.InstrD, // instruction from IFU
|
||||
.ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory
|
||||
.ForwardedSrcAE, // Integer input being processed (from IEU)
|
||||
.StallE, .StallM, .StallW, // stall signals from HZU
|
||||
//.TrapM,
|
||||
.FlushE, .FlushM, .FlushW, // flush signals from HZU
|
||||
.RdE, .RdM, .RdW, // which FP register to write to (from IEU)
|
||||
.STATUS_FS, // is floating-point enabled?
|
||||
.FRegWriteM, // FP register write enable
|
||||
.FpLoadStoreM,
|
||||
.ForwardedSrcBE, // Integer input for intdiv
|
||||
.Funct3E, .Funct3M, .IntDivE, .W64E, // Integer flags and functions
|
||||
.FPUStallD, // Stall the decode stage
|
||||
.FWriteIntE, .FCvtIntE, // integer register write enable, conversion operation
|
||||
.FWriteDataM, // Data to be written to memory
|
||||
.FIntResM, // data to be written to integer register
|
||||
.FCvtIntResW, // fp -> int conversion result to be stored in int register
|
||||
.FCvtIntW, // fpu result selection
|
||||
.FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
|
||||
.IllegalFPUInstrM, // Is the instruction an illegal fpu instruction
|
||||
.SetFflagsM, // FPU flags (to privileged unit)
|
||||
.FIntDivResultW
|
||||
); // floating point unit
|
||||
end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
|
||||
assign FPUStallD = 0;
|
||||
assign FWriteIntE = 0;
|
||||
assign FCvtIntE = 0;
|
||||
assign FIntResM = 0;
|
||||
assign FCvtIntW = 0;
|
||||
assign FDivBusyE = 0;
|
||||
assign IllegalFPUInstrM = 1;
|
||||
assign SetFflagsM = 0;
|
||||
assign FpLoadStoreM = 0;
|
||||
end
|
||||
// multiply/divide unit
|
||||
if (`M_SUPPORTED) begin:mdu
|
||||
mdu mdu(.clk, .reset,
|
||||
.ForwardedSrcAE, .ForwardedSrcBE,
|
||||
.Funct3E, .Funct3M, .IntDivE, .W64E,
|
||||
.MDUResultW, .DivBusyE,
|
||||
.StallM, .StallW, .FlushE, .FlushM, .FlushW);
|
||||
end else begin // no M instructions supported
|
||||
assign MDUResultW = 0;
|
||||
assign DivBusyE = 0;
|
||||
end
|
||||
|
||||
// floating point unit
|
||||
if (`F_SUPPORTED) begin:fpu
|
||||
fpu fpu(
|
||||
.clk, .reset,
|
||||
.FRM_REGW, // Rounding mode from CSR
|
||||
.InstrD, // instruction from IFU
|
||||
.ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory
|
||||
.ForwardedSrcAE, // Integer input being processed (from IEU)
|
||||
.StallE, .StallM, .StallW, // stall signals from HZU
|
||||
//.TrapM,
|
||||
.FlushE, .FlushM, .FlushW, // flush signals from HZU
|
||||
.RdE, .RdM, .RdW, // which FP register to write to (from IEU)
|
||||
.STATUS_FS, // is floating-point enabled?
|
||||
.FRegWriteM, // FP register write enable
|
||||
.FpLoadStoreM,
|
||||
.ForwardedSrcBE, // Integer input for intdiv
|
||||
.Funct3E, .Funct3M, .IntDivE, .W64E, // Integer flags and functions
|
||||
.FPUStallD, // Stall the decode stage
|
||||
.FWriteIntE, .FCvtIntE, // integer register write enable, conversion operation
|
||||
.FWriteDataM, // Data to be written to memory
|
||||
.FIntResM, // data to be written to integer register
|
||||
.FCvtIntResW, // fp -> int conversion result to be stored in int register
|
||||
.FCvtIntW, // fpu result selection
|
||||
.FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
|
||||
.IllegalFPUInstrM, // Is the instruction an illegal fpu instruction
|
||||
.SetFflagsM, // FPU flags (to privileged unit)
|
||||
.FIntDivResultW);
|
||||
end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
|
||||
assign FPUStallD = 0;
|
||||
assign FWriteIntE = 0;
|
||||
assign FCvtIntE = 0;
|
||||
assign FIntResM = 0;
|
||||
assign FCvtIntW = 0;
|
||||
assign FDivBusyE = 0;
|
||||
assign IllegalFPUInstrM = 1;
|
||||
assign SetFflagsM = 0;
|
||||
assign FpLoadStoreM = 0;
|
||||
end
|
||||
endmodule
|
||||
|
||||
Loading…
Reference in New Issue
Block a user