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If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write. Then transition to ReadHold. This cause the d$ flush to go high while in ReadHold. The solution is to ensure the cache continues to assert Stall while in WriteLine state. There was a second issue also. The D$ flush asserted FlushD which flushed the I$ invalidate. Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache. |
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| config | ||
| misc | ||
| regression | ||
| src | ||
| testbench | ||
| radixcopiesmultiregression.sh | ||