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csr cleanup
This commit is contained in:
David Harris
parent
e4f4b31896
commit
97bddf0d54
@ -198,44 +198,49 @@ module csr #(parameter
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///////////////////////////////////////////
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csri csri(.clk, .reset, .InstrValidNotFlushedM,
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.CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM,
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.MExtInt, .SExtInt, .MTimerInt, .MSwInt,
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.MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
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.CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM,
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.MExtInt, .SExtInt, .MTimerInt, .MSwInt,
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.MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
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csrsr csrsr(.clk, .reset, .StallW,
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.WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM,
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.TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW,
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.mretM, .sretM, .WriteFRMM, .WriteFFLAGSM, .CSRWriteValM, .SelHPTW,
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.MSTATUS_REGW, .SSTATUS_REGW, .MSTATUSH_REGW,
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.STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TW,
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.STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM,
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.STATUS_FS, .BigEndianM);
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csrc counters(.clk, .reset, .StallE, .StallM, .FlushM,
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.InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM,
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.DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,
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.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
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.CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
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.MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
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.MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM);
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.WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM,
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.TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW,
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.mretM, .sretM, .WriteFRMM, .WriteFFLAGSM, .CSRWriteValM, .SelHPTW,
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.MSTATUS_REGW, .SSTATUS_REGW, .MSTATUSH_REGW,
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.STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TW,
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.STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM,
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.STATUS_FS, .BigEndianM);
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csrm csrm(.clk, .reset, .InstrValidNotFlushedM,
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.CSRMWriteM, .MTrapM, .CSRAdrM,
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.NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, .MSTATUSH_REGW,
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.CSRWriteValM, .CSRMReadValM, .MTVEC_REGW,
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.MEPC_REGW, .MCOUNTEREN_REGW, .MCOUNTINHIBIT_REGW,
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.MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM,
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.IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM);
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.CSRMWriteM, .MTrapM, .CSRAdrM,
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.NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, .MSTATUSH_REGW,
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.CSRWriteValM, .CSRMReadValM, .MTVEC_REGW,
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.MEPC_REGW, .MCOUNTEREN_REGW, .MCOUNTINHIBIT_REGW,
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.MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM,
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.IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM);
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csrs csrs(.clk, .reset, .InstrValidNotFlushedM,
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.CSRSWriteM, .STrapM, .CSRAdrM,
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.NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW,
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.STATUS_TVM, .CSRWriteValM, .PrivilegeModeW,
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.CSRSReadValM, .STVEC_REGW, .SEPC_REGW,
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.SCOUNTEREN_REGW,
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.SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
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.WriteSSTATUSM, .IllegalCSRSAccessM);
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.CSRSWriteM, .STrapM, .CSRAdrM,
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.NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW,
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.STATUS_TVM, .CSRWriteValM, .PrivilegeModeW,
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.CSRSReadValM, .STVEC_REGW, .SEPC_REGW,
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.SCOUNTEREN_REGW,
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.SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
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.WriteSSTATUSM, .IllegalCSRSAccessM);
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csru csru(.clk, .reset, .InstrValidNotFlushedM,
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.CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM,
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.SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM,
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.IllegalCSRUAccessM);
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.CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM,
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.SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM,
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.IllegalCSRUAccessM);
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if (`ZICOUNTERS_SUPPORTED) begin:counters
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csrc counters(.clk, .reset, .StallE, .StallM, .FlushM,
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.InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM,
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.DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,
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.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
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.CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
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.MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
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.MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM);
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end else begin
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assign CSRCReadValM = 0;
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assign IllegalCSRCAccessM = 1; // counters aren't enabled
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end
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// merge CSR Reads
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assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM;
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@ -39,127 +39,122 @@ module csrc #(parameter
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TIME = 12'hC01,
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TIMEH = 12'hC81
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) (
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input logic clk, reset,
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input logic StallE, StallM,
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input logic FlushM,
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input logic InstrValidNotFlushedM, LoadStallD, CSRMWriteM,
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input logic DirPredictionWrongM,
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input logic BTBPredPCWrongM,
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input logic RASPredPCWrongM,
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input logic PredictionInstrClassWrongM,
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input logic [3:0] InstrClassM,
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input logic DCacheMiss,
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input logic DCacheAccess,
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input logic ICacheMiss,
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input logic ICacheAccess,
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input logic [11:0] CSRAdrM,
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input logic [1:0] PrivilegeModeW,
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input logic [`XLEN-1:0] CSRWriteValM,
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input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW,
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input logic [63:0] MTIME_CLINT,
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output logic [`XLEN-1:0] CSRCReadValM,
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output logic IllegalCSRCAccessM
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input logic clk, reset,
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input logic StallE, StallM,
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input logic FlushM,
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input logic InstrValidNotFlushedM, LoadStallD, CSRMWriteM,
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input logic DirPredictionWrongM,
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input logic BTBPredPCWrongM,
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input logic RASPredPCWrongM,
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input logic PredictionInstrClassWrongM,
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input logic [3:0] InstrClassM,
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input logic DCacheMiss,
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input logic DCacheAccess,
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input logic ICacheMiss,
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input logic ICacheAccess,
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input logic [11:0] CSRAdrM,
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input logic [1:0] PrivilegeModeW,
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input logic [`XLEN-1:0] CSRWriteValM,
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input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW,
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input logic [63:0] MTIME_CLINT,
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output logic [`XLEN-1:0] CSRCReadValM,
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output logic IllegalCSRCAccessM
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);
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if (`ZICOUNTERS_SUPPORTED) begin:counters
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logic [4:0] CounterNumM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0];
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logic [`XLEN-1:0] HPMCOUNTERH_REGW[`COUNTERS-1:0];
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logic LoadStallE, LoadStallM;
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logic [`COUNTERS-1:0] WriteHPMCOUNTERM;
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logic [`COUNTERS-1:0] CounterEvent;
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logic [63:0] HPMCOUNTERPlusM[`COUNTERS-1:0];
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logic [`XLEN-1:0] NextHPMCOUNTERM[`COUNTERS-1:0];
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genvar i;
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logic [4:0] CounterNumM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0];
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logic [`XLEN-1:0] HPMCOUNTERH_REGW[`COUNTERS-1:0];
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logic LoadStallE, LoadStallM;
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logic [`COUNTERS-1:0] WriteHPMCOUNTERM;
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logic [`COUNTERS-1:0] CounterEvent;
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logic [63:0] HPMCOUNTERPlusM[`COUNTERS-1:0];
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logic [`XLEN-1:0] NextHPMCOUNTERM[`COUNTERS-1:0];
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genvar i;
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// Interface signals
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flopenrc #(1) LoadStallEReg(.clk, .reset, .clear(1'b0), .en(~StallE), .d(LoadStallD), .q(LoadStallE)); // don't flush the load stall during a load stall.
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flopenrc #(1) LoadStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(LoadStallE), .q(LoadStallM));
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// Determine when to increment each counter
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assign CounterEvent[0] = 1'b1; // MCYCLE always increments
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assign CounterEvent[1] = 1'b0; // Counter 1 doesn't exist
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assign CounterEvent[2] = InstrValidNotFlushedM;
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if(`QEMU) begin: cevent // No other performance counters in QEMU
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assign CounterEvent[`COUNTERS-1:3] = 0;
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end else begin: cevent // User-defined counters
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assign CounterEvent[3] = LoadStallM; // don't want to suppress on flush as this only happens if flushed.
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assign CounterEvent[4] = DirPredictionWrongM & InstrValidNotFlushedM;
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assign CounterEvent[5] = InstrClassM[0] & InstrValidNotFlushedM;
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assign CounterEvent[6] = BTBPredPCWrongM & InstrValidNotFlushedM;
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assign CounterEvent[7] = (InstrClassM[3] | InstrClassM[1]) & InstrValidNotFlushedM;
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assign CounterEvent[8] = RASPredPCWrongM & InstrValidNotFlushedM;
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assign CounterEvent[9] = InstrClassM[2] & InstrValidNotFlushedM;
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assign CounterEvent[10] = PredictionInstrClassWrongM & InstrValidNotFlushedM;
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assign CounterEvent[11] = DCacheAccess;
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assign CounterEvent[12] = DCacheMiss;
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assign CounterEvent[13] = ICacheAccess;
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assign CounterEvent[14] = ICacheMiss;
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assign CounterEvent[`COUNTERS-1:15] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
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end
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// Counter update and write logic
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for (i = 0; i < `COUNTERS; i = i+1) begin:cntr
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assign WriteHPMCOUNTERM[i] = CSRMWriteM & (CSRAdrM == MHPMCOUNTERBASE + i);
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assign NextHPMCOUNTERM[i][`XLEN-1:0] = WriteHPMCOUNTERM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][`XLEN-1:0];
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always_ff @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
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if (reset) HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 0;
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else HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERM[i];
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if (`XLEN==32) begin // write high and low separately
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logic [`COUNTERS-1:0] WriteHPMCOUNTERHM;
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logic [`XLEN-1:0] NextHPMCOUNTERHM[`COUNTERS-1:0];
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assign HPMCOUNTERPlusM[i] = {HPMCOUNTERH_REGW[i], HPMCOUNTER_REGW[i]} + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
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assign WriteHPMCOUNTERHM[i] = CSRMWriteM & (CSRAdrM == MHPMCOUNTERHBASE + i);
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assign NextHPMCOUNTERHM[i] = WriteHPMCOUNTERHM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][63:32];
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always_ff @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
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if (reset) HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 0;
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else HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERHM[i];
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end else begin // XLEN=64; write entire register
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assign HPMCOUNTERPlusM[i] = HPMCOUNTER_REGW[i] + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
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end
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end
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// Read Counters, or cause excepiton if insufficient privilege in light of COUNTEREN flags
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assign CounterNumM = CSRAdrM[4:0]; // which counter to read?
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always_comb
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if (PrivilegeModeW == `M_MODE |
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MCOUNTEREN_REGW[CounterNumM] & (!`S_SUPPORTED | PrivilegeModeW == `S_MODE | SCOUNTEREN_REGW[CounterNumM])) begin
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IllegalCSRCAccessM = 0;
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if (`XLEN==64) begin // 64-bit counter reads
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// Veri lator doesn't realize this only occurs for XLEN=64
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/* verilator lint_off WIDTH */
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if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT; // TIME register is a shadow of the memory-mapped MTIME from the CLINT
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/* verilator lint_on WIDTH */
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else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
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else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
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else begin
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CSRCReadValM = 0;
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IllegalCSRCAccessM = 1; // requested CSR doesn't exist
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end
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end else begin // 32-bit counter reads
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// Veri lator doesn't realize this only occurs for XLEN=32
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/* verilator lint_off WIDTH */
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if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT
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else if (CSRAdrM == TIMEH) CSRCReadValM = MTIME_CLINT[63:32];
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/* verilator lint_on WIDTH */
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else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
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else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
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else if (CSRAdrM >= MHPMCOUNTERHBASE & CSRAdrM < MHPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
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else if (CSRAdrM >= HPMCOUNTERHBASE & CSRAdrM < HPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
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else begin
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CSRCReadValM = 0;
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IllegalCSRCAccessM = 1; // requested CSR doesn't exist
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end
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end
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end else begin
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CSRCReadValM = 0;
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IllegalCSRCAccessM = 1; // no privileges for this csr
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end
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end else begin
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assign CSRCReadValM = 0;
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assign IllegalCSRCAccessM = 1; // counters aren't enabled
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// Interface signals
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flopenrc #(1) LoadStallEReg(.clk, .reset, .clear(1'b0), .en(~StallE), .d(LoadStallD), .q(LoadStallE)); // don't flush the load stall during a load stall.
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flopenrc #(1) LoadStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(LoadStallE), .q(LoadStallM));
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// Determine when to increment each counter
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assign CounterEvent[0] = 1'b1; // MCYCLE always increments
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assign CounterEvent[1] = 1'b0; // Counter 1 doesn't exist
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assign CounterEvent[2] = InstrValidNotFlushedM;
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if(`QEMU) begin: cevent // No other performance counters in QEMU
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assign CounterEvent[`COUNTERS-1:3] = 0;
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end else begin: cevent // User-defined counters
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assign CounterEvent[3] = LoadStallM; // don't want to suppress on flush as this only happens if flushed.
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assign CounterEvent[4] = DirPredictionWrongM & InstrValidNotFlushedM;
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assign CounterEvent[5] = InstrClassM[0] & InstrValidNotFlushedM;
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assign CounterEvent[6] = BTBPredPCWrongM & InstrValidNotFlushedM;
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assign CounterEvent[7] = (InstrClassM[3] | InstrClassM[1]) & InstrValidNotFlushedM;
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assign CounterEvent[8] = RASPredPCWrongM & InstrValidNotFlushedM;
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assign CounterEvent[9] = InstrClassM[2] & InstrValidNotFlushedM;
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assign CounterEvent[10] = PredictionInstrClassWrongM & InstrValidNotFlushedM;
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assign CounterEvent[11] = DCacheAccess;
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assign CounterEvent[12] = DCacheMiss;
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assign CounterEvent[13] = ICacheAccess;
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assign CounterEvent[14] = ICacheMiss;
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assign CounterEvent[`COUNTERS-1:15] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
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end
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// Counter update and write logic
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for (i = 0; i < `COUNTERS; i = i+1) begin:cntr
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assign WriteHPMCOUNTERM[i] = CSRMWriteM & (CSRAdrM == MHPMCOUNTERBASE + i);
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assign NextHPMCOUNTERM[i][`XLEN-1:0] = WriteHPMCOUNTERM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][`XLEN-1:0];
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always_ff @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
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if (reset) HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 0;
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else HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERM[i];
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if (`XLEN==32) begin // write high and low separately
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logic [`COUNTERS-1:0] WriteHPMCOUNTERHM;
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logic [`XLEN-1:0] NextHPMCOUNTERHM[`COUNTERS-1:0];
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assign HPMCOUNTERPlusM[i] = {HPMCOUNTERH_REGW[i], HPMCOUNTER_REGW[i]} + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
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assign WriteHPMCOUNTERHM[i] = CSRMWriteM & (CSRAdrM == MHPMCOUNTERHBASE + i);
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assign NextHPMCOUNTERHM[i] = WriteHPMCOUNTERHM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][63:32];
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always_ff @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
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if (reset) HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 0;
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else HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERHM[i];
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end else begin // XLEN=64; write entire register
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assign HPMCOUNTERPlusM[i] = HPMCOUNTER_REGW[i] + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
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end
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end
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// Read Counters, or cause excepiton if insufficient privilege in light of COUNTEREN flags
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assign CounterNumM = CSRAdrM[4:0]; // which counter to read?
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always_comb
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if (PrivilegeModeW == `M_MODE |
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MCOUNTEREN_REGW[CounterNumM] & (!`S_SUPPORTED | PrivilegeModeW == `S_MODE | SCOUNTEREN_REGW[CounterNumM])) begin
|
||||
IllegalCSRCAccessM = 0;
|
||||
if (`XLEN==64) begin // 64-bit counter reads
|
||||
// Veri lator doesn't realize this only occurs for XLEN=64
|
||||
/* verilator lint_off WIDTH */
|
||||
if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT; // TIME register is a shadow of the memory-mapped MTIME from the CLINT
|
||||
/* verilator lint_on WIDTH */
|
||||
else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
|
||||
else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
|
||||
else begin
|
||||
CSRCReadValM = 0;
|
||||
IllegalCSRCAccessM = 1; // requested CSR doesn't exist
|
||||
end
|
||||
end else begin // 32-bit counter reads
|
||||
// Veri lator doesn't realize this only occurs for XLEN=32
|
||||
/* verilator lint_off WIDTH */
|
||||
if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT
|
||||
else if (CSRAdrM == TIMEH) CSRCReadValM = MTIME_CLINT[63:32];
|
||||
/* verilator lint_on WIDTH */
|
||||
else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
|
||||
else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
|
||||
else if (CSRAdrM >= MHPMCOUNTERHBASE & CSRAdrM < MHPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
|
||||
else if (CSRAdrM >= HPMCOUNTERHBASE & CSRAdrM < HPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
|
||||
else begin
|
||||
CSRCReadValM = 0;
|
||||
IllegalCSRCAccessM = 1; // requested CSR doesn't exist
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
CSRCReadValM = 0;
|
||||
IllegalCSRCAccessM = 1; // no privileges for this csr
|
||||
end
|
||||
endmodule
|
||||
|
||||
// To Do:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user