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https://github.com/openhwgroup/cvw
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ebu cleanup
This commit is contained in:
David Harris
parent
17fd2d2a3b
commit
94d01d292e
@ -32,41 +32,41 @@
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`include "wally-config.vh"
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module controllerinputstage #(parameter SAVE_ENABLED = 1)
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(input logic HCLK,
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input logic HRESETn,
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input logic Save, Restore, Disable,
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output logic Request,
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// controller input
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input logic HWRITEIn,
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input logic [2:0] HSIZEIn,
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input logic [2:0] HBURSTIn,
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input logic [1:0] HTRANSIn,
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input logic [`PA_BITS-1:0] HADDRIn,
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output logic HREADYOut,
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// controller output
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output logic HWRITEOut,
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output logic [2:0] HSIZEOut,
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output logic [2:0] HBURSTOut,
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output logic [1:0] HTRANSOut,
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output logic [`PA_BITS-1:0] HADDROut,
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input logic HREADYIn
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);
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module controllerinputstage #(parameter SAVE_ENABLED = 1) (
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input logic HCLK,
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input logic HRESETn,
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input logic Save, Restore, Disable,
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output logic Request,
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// controller input
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input logic HWRITEIn,
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input logic [2:0] HSIZEIn,
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input logic [2:0] HBURSTIn,
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input logic [1:0] HTRANSIn,
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input logic [`PA_BITS-1:0] HADDRIn,
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output logic HREADYOut,
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// controller output
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output logic HWRITEOut,
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output logic [2:0] HSIZEOut,
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output logic [2:0] HBURSTOut,
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output logic [1:0] HTRANSOut,
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output logic [`PA_BITS-1:0] HADDROut,
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input logic HREADYIn
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);
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logic HWRITESave;
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logic [2:0] HSIZESave;
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logic [2:0] HBURSTSave;
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logic [1:0] HTRANSSave;
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logic [`PA_BITS-1:0] HADDRSave;
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logic HWRITESave;
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logic [2:0] HSIZESave;
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logic [2:0] HBURSTSave;
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logic [1:0] HTRANSSave;
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logic [`PA_BITS-1:0] HADDRSave;
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if (SAVE_ENABLED) begin
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flopenr #(1+3+3+2+`PA_BITS) SaveReg(HCLK, ~HRESETn, Save,
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{HWRITEIn, HSIZEIn, HBURSTIn, HTRANSIn, HADDRIn},
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{HWRITESave, HSIZESave, HBURSTSave, HTRANSSave, HADDRSave});
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mux2 #(1+3+3+2+`PA_BITS) RestorMux({HWRITEIn, HSIZEIn, HBURSTIn, HTRANSIn, HADDRIn},
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{HWRITESave, HSIZESave, HBURSTSave, HTRANSSave, HADDRSave},
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Restore,
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{HWRITEOut, HSIZEOut, HBURSTOut, HTRANSOut, HADDROut});
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flopenr #(1+3+3+2+`PA_BITS) SaveReg(HCLK, ~HRESETn, Save,
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{HWRITEIn, HSIZEIn, HBURSTIn, HTRANSIn, HADDRIn},
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{HWRITESave, HSIZESave, HBURSTSave, HTRANSSave, HADDRSave});
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mux2 #(1+3+3+2+`PA_BITS) RestorMux({HWRITEIn, HSIZEIn, HBURSTIn, HTRANSIn, HADDRIn},
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{HWRITESave, HSIZESave, HBURSTSave, HTRANSSave, HADDRSave},
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Restore,
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{HWRITEOut, HSIZEOut, HBURSTOut, HTRANSOut, HADDROut});
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end else begin
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assign HWRITEOut = HWRITEIn;
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assign HSIZEOut = HSIZEIn;
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@ -32,42 +32,41 @@
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`include "wally-config.vh"
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module ebu
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(
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input logic clk, reset,
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// Signals from IFU
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input logic [`PA_BITS-1:0] IFUHADDR,
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input logic [2:0] IFUHSIZE,
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input logic [2:0] IFUHBURST,
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input logic [1:0] IFUHTRANS,
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output logic IFUHREADY,
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// Signals from LSU
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input logic [`PA_BITS-1:0] LSUHADDR,
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input logic [`XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN
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input logic [`XLEN/8-1:0] LSUHWSTRB,
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input logic [2:0] LSUHSIZE,
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input logic [2:0] LSUHBURST,
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input logic [1:0] LSUHTRANS,
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input logic LSUHWRITE,
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output logic LSUHREADY,
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// add LSUHWSTRB ***
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// AHB-Lite external signals
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(* mark_debug = "true" *) input logic HREADY, HRESP,
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(* mark_debug = "true" *) output logic HCLK, HRESETn,
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(* mark_debug = "true" *) output logic [`PA_BITS-1:0] HADDR, // *** one day switch to a different bus that supports the full physical address
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(* mark_debug = "true" *) output logic [`AHBW-1:0] HWDATA,
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(* mark_debug = "true" *) output logic [`XLEN/8-1:0] HWSTRB,
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(* mark_debug = "true" *) output logic HWRITE,
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(* mark_debug = "true" *) output logic [2:0] HSIZE,
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(* mark_debug = "true" *) output logic [2:0] HBURST,
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(* mark_debug = "true" *) output logic [3:0] HPROT,
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(* mark_debug = "true" *) output logic [1:0] HTRANS,
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(* mark_debug = "true" *) output logic HMASTLOCK
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);
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module ebu (
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input logic clk, reset,
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// Signals from IFU
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input logic [`PA_BITS-1:0] IFUHADDR,
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input logic [2:0] IFUHSIZE,
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input logic [2:0] IFUHBURST,
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input logic [1:0] IFUHTRANS,
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output logic IFUHREADY,
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// Signals from LSU
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input logic [`PA_BITS-1:0] LSUHADDR,
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input logic [`XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN
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input logic [`XLEN/8-1:0] LSUHWSTRB,
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input logic [2:0] LSUHSIZE,
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input logic [2:0] LSUHBURST,
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input logic [1:0] LSUHTRANS,
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input logic LSUHWRITE,
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output logic LSUHREADY,
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// add LSUHWSTRB ***
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// AHB-Lite external signals
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(* mark_debug = "true" *) input logic HREADY, HRESP,
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(* mark_debug = "true" *) output logic HCLK, HRESETn,
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(* mark_debug = "true" *) output logic [`PA_BITS-1:0] HADDR,
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(* mark_debug = "true" *) output logic [`AHBW-1:0] HWDATA,
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(* mark_debug = "true" *) output logic [`XLEN/8-1:0] HWSTRB,
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(* mark_debug = "true" *) output logic HWRITE,
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(* mark_debug = "true" *) output logic [2:0] HSIZE,
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(* mark_debug = "true" *) output logic [2:0] HBURST,
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(* mark_debug = "true" *) output logic [3:0] HPROT,
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(* mark_debug = "true" *) output logic [1:0] HTRANS,
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(* mark_debug = "true" *) output logic HMASTLOCK
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);
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typedef enum logic [1:0] {IDLE, ARBITRATE} statetype;
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statetype CurrState, NextState;
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statetype CurrState, NextState;
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logic LSUDisable, LSUSelect;
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logic IFUSave, IFURestore, IFUDisable, IFUSelect;
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@ -98,7 +97,6 @@ module ebu
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assign HCLK = clk;
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assign HRESETn = ~reset;
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// if two requests come in at once pick one to select and save the others Address phase
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// inputs. Abritration scheme is LSU always goes first.
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@ -137,21 +135,16 @@ module ebu
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flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextState, IDLE, CurrState);
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always_comb
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case (CurrState)
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IDLE: if (both) NextState = ARBITRATE;
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else NextState = IDLE;
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ARBITRATE: if (HREADY & FinalBeatD & ~(LSUReq & IFUReq)) NextState = IDLE;
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else NextState = ARBITRATE;
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default: NextState = IDLE;
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IDLE: if (both) NextState = ARBITRATE;
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else NextState = IDLE;
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ARBITRATE: if (HREADY & FinalBeatD & ~(LSUReq & IFUReq)) NextState = IDLE;
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else NextState = ARBITRATE;
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default: NextState = IDLE;
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endcase
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// This part is only used when burst mode is supported.
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// Controller needs to count beats.
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flopenr #(4)
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BeatCountReg(.clk(HCLK),
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.reset(~HRESETn | CntReset | FinalBeat),
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.en(BeatCntEn),
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.d(NextBeatCount),
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.q(BeatCount));
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flopenr #(4) BeatCountReg(HCLK, ~HRESETn | CntReset | FinalBeat, BeatCntEn, NextBeatCount, BeatCount);
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assign NextBeatCount = BeatCount + 1'b1;
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assign CntReset = NextState == IDLE;
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@ -159,12 +152,7 @@ module ebu
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assign BeatCntEn = (NextState == ARBITRATE & HREADY);
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// Used to store data from data phase of AHB.
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flopenr #(1)
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FinalBeatReg(.clk(HCLK),
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.reset(~HRESETn | CntReset),
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.en(BeatCntEn),
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.d(FinalBeat),
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.q(FinalBeatD));
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flopenr #(1) FinalBeatReg(HCLK, ~HRESETn | CntReset, BeatCntEn, FinalBeat, FinalBeatD);
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// unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST.
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always_comb begin
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@ -176,7 +164,6 @@ module ebu
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default: Threshold = 4'b0000; // INCR without end.
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endcase
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end
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// end of burst mode.
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// basic arb always selects LSU when both
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// replace this block for more sophisticated arbitration as needed.
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@ -191,5 +178,4 @@ module ebu
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flopr #(1) ifureqreg(clk, ~HRESETn, IFUReq, IFUReqD);
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endmodule
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