David Harris
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bddd2d573e
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Shortened path to PCSrcE in logger to avoid problematic hierarchical reference
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2023-11-05 07:06:53 -08:00 |
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David Harris
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9c4a7866b8
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Fixed Svnapot_page_mask for imperas.ic
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2023-11-05 06:51:01 -08:00 |
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David Harris
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b0dbf3a984
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Testbench fixes to add SPI and make string pp static in testbench.fp to solve compiler issue
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2023-11-04 20:36:05 -07:00 |
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David Harris
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568aa3c4a6
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Verilator improvements
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2023-11-04 03:21:07 -07:00 |
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David Harris
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4de21c206f
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-03 16:04:10 -07:00 |
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David Harris
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d067b735e8
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Merge pull request #454 from naichewa/spi
add SPI to cvw/main
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2023-11-03 16:02:57 -07:00 |
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naichewa
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75f1c07022
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merge main, pull /A/ tests
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2023-11-03 13:16:19 -07:00 |
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naichewa
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6cdeb671bb
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Merge branch 'main' into spi
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2023-11-03 13:15:15 -07:00 |
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David Harris
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7a56a66927
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set default USE_SRAM=0 in memories; cleaned up synthesis script grep for cvw_t
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2023-11-03 06:37:05 -07:00 |
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David Harris
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1f2899de14
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Modified rams to take USE_SRAM rather than P to facilitate synthesis
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2023-11-03 05:44:13 -07:00 |
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David Harris
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dd072c80f2
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Updated testbenches to capture InstrM because it may be optimized out of IFU
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2023-11-03 05:24:15 -07:00 |
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David Harris
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402538e13c
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Temporary fix of InstrM to prevent testbench hanging
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2023-11-03 04:59:44 -07:00 |
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David Harris
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09aebbf252
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Fixed regression error of watchdog timeout when PCM is optimized out of the IFU
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2023-11-03 04:38:27 -07:00 |
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naichewa
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4651b807ed
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added test cases
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2023-11-02 15:43:08 -07:00 |
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naichewa
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29e42b21df
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added test cases
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2023-11-02 15:42:28 -07:00 |
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Rose Thompson
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455b78362c
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Merge pull request #449 from davidharrishmc/dev
Synthesis cleanup
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2023-11-02 12:26:55 -05:00 |
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David Harris
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bf65ce0f9f
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Removed .gitattributes
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2023-11-01 17:50:44 -07:00 |
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naichewa
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a08356fdaa
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correct exclusion tags and reset testbench
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2023-11-01 10:34:39 -07:00 |
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naichewa
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e3d8162279
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harris code review 3
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2023-11-01 10:14:15 -07:00 |
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David Harris
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31d9ec08cb
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Improved comments about memory read paths
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2023-11-01 07:00:17 -07:00 |
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naichewa
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9aa8a7af3e
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comments, more test cases
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2023-11-01 01:26:34 -07:00 |
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naichewa
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fefb5adb8f
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code review harris
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2023-10-31 12:27:41 -07:00 |
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David Harris
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dccd7bf5ee
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Fixes to config extraction
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2023-10-31 06:27:55 -07:00 |
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David Harris
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5112bfed19
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130 nm synthesis script improvements
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2023-10-30 20:57:35 -07:00 |
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David Harris
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680fb3f30b
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Conditionally instantiate hardware in ifu
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2023-10-30 20:55:00 -07:00 |
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David Harris
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afabc52b61
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Gated InstrOrigM and PCMReg when not needed
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2023-10-30 20:05:37 -07:00 |
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David Harris
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2d17a991d8
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rom1p1r code cleanup
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2023-10-30 19:47:49 -07:00 |
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David Harris
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3f7c67882f
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rom1p1r code cleanup
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2023-10-30 19:46:38 -07:00 |
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David Harris
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90a178e31e
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Made 2-bit AdrReg conditional on being needed
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2023-10-30 19:13:43 -07:00 |
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naichewa
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7dd3f24d6c
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Merge branch 'main' into spi
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2023-10-30 17:01:41 -07:00 |
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naichewa
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2330f4ee63
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hardware interlock
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2023-10-30 17:00:20 -07:00 |
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Rose Thompson
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89de8cd23c
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Merge pull request #445 from davidharrishmc/dev
Fix issue 444; no delegating misaligned instructions if they can't happen
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2023-10-30 12:25:42 -05:00 |
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David Harris
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f6a7f707bd
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Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
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2023-10-30 09:56:17 -07:00 |
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David Harris
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27b8ebb9bd
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Fix issue 444 by preventing delegation of misaligned instructions when compressed instructions are supported.
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2023-10-30 07:06:34 -07:00 |
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Rose Thompson
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50a1d731c0
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Merge pull request #443 from davidharrishmc/dev
Wrapper synthesis fix.
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2023-10-27 09:25:06 -05:00 |
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David Harris
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09c4aaa5d9
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Fixed reporting of timing on modules with wrappers
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2023-10-26 20:14:14 -07:00 |
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David Harris
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734bf021d7
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-10-26 19:02:05 -07:00 |
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David Harris
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8cf81a2bb8
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Merge pull request #441 from ross144/main
Fixed issues #200
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2023-10-26 10:26:58 -07:00 |
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Rose Thompson
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06b5a92eff
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Updated comments about Interrupt and wfi.
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2023-10-26 12:24:36 -05:00 |
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Rose Thompson
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4cd0584a11
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Forgot to include this file in the last commit.
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2023-10-26 12:20:42 -05:00 |
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Rose Thompson
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14f8b4849f
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-10-26 12:15:22 -05:00 |
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Rose Thompson
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3322ff915e
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Cleaned up the implementation changes for wfi.
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2023-10-24 23:11:48 -05:00 |
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Rose Thompson
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c58f04c901
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This version passes the regression test and solves issue #200. wfi's implemenation is changed so that wfi does not take an interrupt in the Memory stage. Instead it advances to the Writeback stage then traps.
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2023-10-24 22:58:26 -05:00 |
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Rose Thompson
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c61526d034
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Possible fix for wfi.
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2023-10-24 18:08:33 -05:00 |
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David Harris
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3bb7539429
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Fixed warnings of signed conversion and for Design Compiler
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2023-10-24 14:01:43 -07:00 |
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David Harris
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905c5da7a9
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Tested assembly language file for the pause example
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2023-10-24 10:45:41 -07:00 |
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David Harris
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ea571a6e3b
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Merge pull request #439 from ross144/main
Fixes to branch predictor processing scripts.
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2023-10-24 08:31:06 -07:00 |
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Rose Thompson
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bd04ffc0c9
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Fixed bug in bpred-sim.py for btb and class size sweep.
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2023-10-24 10:29:02 -05:00 |
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Rose Thompson
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4fe58fe036
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-10-23 16:14:30 -05:00 |
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Rose Thompson
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ea403e02ff
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Updated bpred-sim.py to take command line options to select between sweeping direction, target, class, or ras prediction.
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2023-10-23 16:09:40 -05:00 |
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