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Fixed reporting of timing on modules with wrappers

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This commit is contained in:
David Harris 2023-10-26 20:14:14 -07:00
parent 734bf021d7
commit 09c4aaa5d9
1 changed files with 13 additions and 0 deletions
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13
synthDC/scripts/synth.tcl
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@ -257,6 +257,19 @@ set write_hier 1 ;# generate hierarchy report
if { $wrapper == 1 } {
set designname [format "%s%s" $my_design "__*"]
current_design $designname
# recreate clock below wrapper level or reporting doesn't work properly
set find_clock [ find port [list $my_clock_pin] ]
if { $find_clock != [list] } {
echo "Found clock!"
set my_clk $my_clock_pin
create_clock -period $my_period $my_clk
set_clock_uncertainty $my_uncertainty [get_clocks $my_clk]
} else {
echo "Did not find clock! Design is probably combinational!"
set my_clk vclk
create_clock -period $my_period -name $my_clk
}
}
# Report Constraint Violators