Rose Thompson
00840e4893
Made the fpga top level configurable between rvvi synth and not.
2024-07-19 17:35:30 -05:00
Rose Thompson
9471dcd296
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.
...
Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
2024-07-19 17:08:47 -05:00
Rose Thompson
0d40b8c933
Cleanup in prep to merge the rvvi branch into main.
2024-07-19 15:48:20 -05:00
Jacob Pease
53b2a51c89
Added tentative spi_send_byte function.
2024-07-19 12:30:32 -05:00
Jacob Pease
34e89e842c
Added initial spi code to fpga/zsbl
2024-07-19 11:35:12 -05:00
Ross Thompson
c72f0fd504
Added csr comparison.
2024-07-11 10:49:06 -05:00
Ross Thompson
abf9da01ab
code cleanup.
2024-07-11 10:41:34 -05:00
Ross Thompson
f0096f5a43
Yay. It's actually working! The FPGA/ImperasDV hybrid is working.
2024-07-10 15:10:37 -05:00
Ross Thompson
e6dc962d11
Yay! the trigger is correctly working now!
2024-07-10 12:05:10 -05:00
Ross Thompson
cf986b5fb8
Really close to having the trigger in module work.
...
Can trigger on the data of the correct frame, but trigger in is still not
working.
2024-07-09 19:04:51 -05:00
Ross Thompson
6734685333
Fixed connection bugs in the top level fpga which preventing sending ethernet frames back to the trigger in unit.
2024-07-09 19:04:18 -05:00
Ross Thompson
e0a1f0e39f
Really close now.
2024-07-09 14:21:43 -05:00
Ross Thompson
e488ee7225
Correctly sending the ethernet frame on a mismatch. Now just need to get vivado to actually trigger.
2024-07-09 14:16:13 -05:00
Ross Thompson
fd170a6583
Getting closer.
2024-07-09 14:09:56 -05:00
Ross Thompson
bf69a2e1cd
Updated to use the newest imperasDV.
2024-07-09 12:30:18 -05:00
Jordan Carlin
7419689359
Update python shebangs to use /usr/bin/env python3 so virtual environment can be used (also aids in general portability)
2024-07-03 20:42:55 -07:00
Ross Thompson
dc97ee5f82
Have some sample code which I know works transmisting a packet.
2024-07-02 09:12:34 -07:00
Ross Thompson
ccf4bb8ddc
Maybe have the incircuit trigger working.
2024-06-26 16:15:46 -07:00
Ross Thompson
612a281f62
Added module to receive ethernet frame and trigger the ila.
2024-06-26 11:05:31 -07:00
Ross Thompson
74189e1e4b
Have vivado triggering the ILA after the mismatch but the latency is way too long.
2024-06-25 17:04:14 -07:00
Ross Thompson
fa26c9a8b5
Added pipe to vivado to create ila trigger from rvvidaemon.
2024-06-25 13:07:46 -07:00
Ross Thompson
249d58244a
It's working!!!!!!
2024-06-20 15:48:30 -07:00
Ross Thompson
1c6ebb86a3
Added some debug code to count frames sent to the ethernet mac and frames sent to the phy.
...
Removed the external reset of the phy and now it always reliably starts in the same way. The first 0x117 frames are always captured.
2024-06-20 12:54:12 -07:00
Ross Thompson
ab1ee3d69b
Removed *** from IFU, lrcs.
2024-06-19 09:40:35 -07:00
Ross Thompson
c5dac4d775
Removed *** from fpga top.
2024-06-19 09:28:21 -07:00
Ross Thompson
93829ce509
Success! We have some instructions comparing across the FPGA and IDV!
...
However I'm still losing ethernet frames.
2024-06-17 13:41:40 -07:00
Ross Thompson
598770da51
Getting much closer to a working version.
2024-06-17 12:37:10 -07:00
Ross Thompson
82b54c0887
Got IDV properly initalized.
2024-06-17 09:15:59 -07:00
Ross Thompson
47523c97ac
Getting closer to figuring out the lost ethernet frame bugs.
2024-06-13 15:46:54 -07:00
Ross Thompson
c9f51df34a
Fixed bug in rvvi reset.
2024-06-12 14:47:32 -07:00
Ross Thompson
323dbd348e
Progress.
2024-06-12 12:54:21 -07:00
Ross Thompson
f5d4db68b1
Modified rvvidaemon to populate a struct with all the relavent fields.
2024-06-12 08:56:16 -07:00
Ross Thompson
3e7d07dfb6
Better.
2024-06-11 17:14:59 -07:00
Ross Thompson
8bce2fc739
Getting closer.
2024-06-11 16:21:53 -07:00
Ross Thompson
c9f3da51cb
getting closer to full reconstruction of rvvi.
2024-06-11 15:35:35 -07:00
Ross Thompson
3d9f796f21
Better parsing of rvvi.
2024-06-11 14:36:34 -07:00
Ross Thompson
563980443a
Merge branch 'main' into rvvi
2024-06-10 18:10:23 -07:00
Ross Thompson
49912589f5
Added rvviApi.h to rvvidaemon.
2024-06-10 17:57:24 -07:00
Ross Thompson
e16cf9d739
Added Makefile to compile rvvidaemon
2024-06-10 16:56:53 -07:00
Rose Thompson
72c1374d9c
Minor code cleanup.
2024-06-04 15:11:57 -05:00
Rose Thompson
f0ed780745
progress.
2024-06-04 15:11:03 -05:00
Rose Thompson
07d66c246c
Update.
2024-06-04 11:59:17 -05:00
Rose Thompson
08ff88f428
On the way towards complete reconstruction of the RVVI trace.
2024-06-04 11:47:46 -05:00
Rose Thompson
80f98b3223
now have a working ethernet daemon to collect frames and partially decode into RVVI.
2024-06-04 10:20:51 -05:00
Jacob Pease
7a417d7a6c
Added true bootloader to fpga/zsbl directory.
2024-05-31 15:28:25 -05:00
Rose Thompson
6a4c8667df
Added new signals to ILA to debug the RVVI tracer.
...
The tracer appears to be stuck and the CPU is never getting out of (into reset).
2024-05-30 16:43:25 -05:00
Rose Thompson
38ddbf860e
Fixed bug with mmcm not generating the 4th clock.
2024-05-30 16:19:28 -05:00
Jacob Pease
3f7659c8ad
Removed old fpgaTop.v file.
2024-05-30 16:15:19 -05:00
Jacob Pease
7ecd1c7d5f
The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.
2024-05-30 15:48:27 -05:00
Rose Thompson
9703055758
The FPGA is synthesizing with the rvvi and ethernet hardware.
2024-05-30 15:37:17 -05:00
Rose Thompson
8123695831
Maded insert_debug_comment.sh compatible with cygwin.
2024-04-22 10:48:34 -05:00
Rose Thompson
3bed733301
Fixed fpga to work with the updated regression changes.
2024-04-22 10:42:01 -05:00
Rose Thompson
c1221e6608
Fixed insert_debug_comment.sh to work with the older version of bash.
2024-04-16 10:55:26 -05:00
Rose Thompson
6097444b5a
Added missing file for compiling the fpga zero stage bootloader.
2024-04-11 10:30:56 -05:00
Rose Thompson
60f96112db
Moved the zero stage boot loader to the fpga directory.
2024-03-01 10:23:55 -06:00
Rose Thompson
cc7f433ce0
Update the fpga scripts to use the new derivative configs.
2024-01-31 13:19:28 -06:00
David Harris
45e2317636
Added Wally github address to header comments
2024-01-29 05:38:11 -08:00
Rose Thompson
7693c5d4e2
Updates to fpga top level.
2023-12-15 15:32:05 -06:00
Rose Thompson
26cd22c388
Replaced fpga's verilog top with system verilog.
2023-12-15 13:42:52 -06:00
Rose Thompson
dab9d7ab3c
Replaced fpga top level verilog with system verilog.
2023-12-15 13:07:08 -06:00
Rose Thompson
34631c54d3
Get's the fpga building again after the git history rewrite.
2023-12-14 17:08:25 -06:00
Jacob Pease
7e494f2d3b
Removed vivado property from rom1p1r.sv. It's now dynamically added using the FPGA makefile.
2023-12-01 18:59:18 -06:00
Jacob Pease
71066cae12
Modified FPGA Makefile to override with relative path. FPGA boots now.
2023-11-30 17:51:15 -06:00
Rose Thompson
b137759b45
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-11-20 10:34:36 -06:00
Rose Thompson
cdd21d6635
Added menvcfg to debugger for checking what linux has configured.
2023-11-19 13:44:22 -06:00
Jacob Pease
87e6a5ccf2
Updated ROM to preload bootloader from file and infer a block ram when building for FPGA.
2023-11-18 19:15:39 -06:00
Jacob Pease
ff73f798ed
Replaced vivado-risc-v addins directory with new SDC repo.
2023-11-16 13:59:12 -06:00
Rose Thompson
d4bc9da085
Fixed another bug in the updated script changes.
2023-11-13 18:12:02 -06:00
Rose Thompson
f8b65f50b0
Fixed bugs in the updated fpga synthe script.
2023-11-13 18:10:22 -06:00
Rose Thompson
d5f0c15b90
Modified the fpga build script to generate it's own config file rather than use the one in config/fpga.
2023-11-13 17:48:28 -06:00
Rose Thompson
6b7ff50a84
Reduced Arty A7 clock speed to 20Mhz to support Zicclsm.
2023-11-13 16:44:02 -06:00
Ross Thompson
d33c966a42
Changed SDC outputs to ensure they are aligned to the falling edge of the divided down clock rather than the processor clock.
2023-10-10 17:46:12 -05:00
Ross Thompson
055e00b8ac
Pushed vcu118 to 71MHz.
2023-08-25 17:04:50 -05:00
Jacob Pease
2bf6207919
Added help option to the flash-sd script.
2023-08-22 13:37:33 -05:00
Jacob Pease
e489ede51d
Merge branch 'main' of github.com:openhwgroup/cvw
2023-08-21 16:10:09 -05:00
David Harris
d801916d97
Merge pull request #383 from ross144/main
...
Adds Zicbom support for D-cache only. I-cache not yet supported. Tests 32 and 64 bit versions. Please rebuild regressions wally32 and wally64. To save rebuild time edit lines 11-12 of tests/riscof/Makefile
2023-08-21 13:32:00 -07:00
Ross Thompson
a16cde3dc6
Removed unused file.
2023-08-21 15:12:59 -05:00
Ross Thompson
1e0f1aeeac
Updated artyA7 debugger to match book.
2023-08-21 14:35:42 -05:00
Jacob Pease
144d93eba4
Added SPDX headers to other probe scripts.
2023-08-16 14:04:25 -05:00
Jacob Pease
f91157fc95
Added SPDX header to probe script.
2023-08-16 13:05:37 -05:00
Jacob Pease
c2f2bef433
Fixed bug caused by errant tab size in probe script.
2023-08-16 12:20:08 -05:00
Jacob Pease
63e901e981
Added probe script to generate a single probe for the fpga.
2023-08-16 12:12:31 -05:00
Ross Thompson
cab40e618f
Updateds to vcu118 constraints and device tree.
2023-08-02 16:51:32 -05:00
Ross Thompson
fb1c1a1832
Added new signals to the vcu118 debug4 ila to help figure out why the new linux build's hptw fails.
2023-08-02 16:14:04 -05:00
Ross Thompson
5790dafdce
Fixed constraint in VCU118.
2023-08-02 13:02:28 -05:00
Ross Thompson
c4ae856f92
Clean up vcu118 synth scripts.
2023-08-01 14:39:33 -05:00
Ross Thompson
06efd2cdde
Pushed performance of arty a7 to 23Mhz.
2023-07-31 14:13:09 -05:00
Jacob Pease
9d33e08dbb
Removed non-existent SDC dependency from VCU targets in FPGA Makefile.
2023-07-27 15:01:20 -05:00
Jacob Pease
b626f2185a
Fixed GPIO pin names in fpgaTop.v
2023-07-25 20:57:04 -05:00
Ross Thompson
b1f7a5768f
Removed all old references to the old flash card controller.
...
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
2023-07-24 15:45:57 -05:00
Ross Thompson
49b87d4550
Merge branch 'main' of github.com:ross144/cvw
2023-07-24 10:47:05 -05:00
Ross Thompson
065e5e98c9
Improved timing constraints for arty a7 to push clock speed to 20Mhz.
2023-07-24 10:46:49 -05:00
Ross Thompson
63afd95ad3
Fixed bugs in boot and new flash card merge. Works with arty a7 now.
2023-07-22 15:52:25 -05:00
Ross Thompson
ab6ef5bb58
At least it simulates and gets through fpga elaboration.
2023-07-21 18:40:26 -05:00
Ross Thompson
a89a1e675c
Merge branch 'boot' into mergeBoot
...
Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Ross Thompson
d04d2afed2
Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card.
2023-07-21 13:06:27 -05:00
Jacob Pease
380d96b359
Working new boot process. Buildroot package for sdc.
2023-07-20 14:15:59 -05:00
Ross Thompson
2752e5de4c
Fixed a bunch of timing constraints for the arty a7 board.
2023-07-19 17:08:16 -05:00
Ross Thompson
97a16f75dc
Fixed typo in fpga top for arty a7.
2023-07-19 11:37:29 -05:00
Ross Thompson
e4d6a9f8c6
Removed all old configuration files.
2023-07-19 10:28:54 -05:00
