Ross Thompson
e1dbe58632
File name change for cachereplacement policy to cacheLRU
2022-11-20 22:35:02 -06:00
Ross Thompson
4e926ba4cf
Signal name changes for LRU.
2022-11-20 22:31:36 -06:00
Ross Thompson
0106777f02
Finally have the correct replacement policy implementation.
2022-11-17 17:36:37 -06:00
Ross Thompson
22ad49eef2
Progress on the cache replacement policy implementation.
2022-11-16 15:35:34 -06:00
Ross Thompson
42111db671
Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr.
2022-11-16 12:36:58 -06:00
Ross Thompson
1f21a2bab1
Created improved cache replacement policy implementation. This version is generic and works for any number of ways. Not fully tested and is currently commented out.
2022-11-16 11:15:34 -06:00
Ross Thompson
b53f8eceef
Renamed Flush to FlushStage in the cache.
2022-11-14 14:11:05 -06:00
Ross Thompson
13e6f7d80b
Changed names of cache signals.
2022-11-13 21:36:12 -06:00
Ross Thompson
8658a25218
Renamed Word to Beat for ahbcacheinterface.
2022-11-09 17:52:50 -06:00
Ross Thompson
be8e0eee1b
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
Ross Thompson
44171c342d
Reduced complexity of logic supressing cache operations.
2022-11-01 15:23:24 -05:00
Ross Thompson
6696624971
comment updates.
2022-10-22 16:28:44 -05:00
Ross Thompson
2c5847b01f
Moving interlockfsm changes to a temporary branch.
...
reduced complexity of cache mux controls.
2022-10-19 15:08:23 -05:00
Ross Thompson
494f8b94f4
Reordered the eviction and fetch in cache so it follows a more logical order.
2022-10-04 17:36:07 -05:00
Ross Thompson
18e739befc
Modified cache lru to not have the delayed write.
2022-10-04 15:14:58 -05:00
Ross Thompson
4062fe56c0
Possible fix to the bus cache interaction.
2022-09-27 11:34:33 -05:00
Ross Thompson
07bb11518e
Found a hidden bug in the cache to bus fsm interlock.
2022-09-26 17:41:30 -05:00
Ross Thompson
0fcc314d06
Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed.
2022-09-26 12:48:26 -05:00
Ross Thompson
38edbde966
Renamed RW signals through the caches, bus interfaces, and IFU/LSU.
...
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
2022-09-23 11:46:53 -05:00
Ross Thompson
cec50ce208
The valid and dirty bits match the SRAM implementation now.
2022-09-22 16:09:09 -05:00
Ross Thompson
b48d6b5e1f
Solved the sram write first / read first issue. Works correctly with read first now.
2022-09-22 14:16:26 -05:00
Ross Thompson
3fb0a13fe2
Moved other SRAMs to generic/mem.
2022-09-21 12:36:03 -05:00
Ross Thompson
ac864a6ca3
Merged together bram1p1rw with sram1p1rw as sram1p1rw.
...
Fixed a major issue with the real SRAM implemenation.
2022-09-21 12:20:00 -05:00
Ross Thompson
c0884ecc63
Modified sram1p1rw to support 3 different implementation styles.
...
SRAM, Read first, and Write first.
2022-09-21 11:26:00 -05:00
Ross Thompson
2c86badeb2
pipelining of fetch into evict AHB requests.
2022-09-13 17:51:55 -05:00
Ross Thompson
7f1ae039b0
Optimization. Able to remove hptw address muxes from the E stage.
2022-09-08 15:51:18 -05:00
Ross Thompson
1b339f0547
Moved files around.
2022-08-31 14:08:06 -05:00
Ross Thompson
8156109add
More cleanup.
2022-08-31 11:12:38 -05:00
Ross Thompson
4b167ad21e
More simplifications.
2022-08-31 10:45:16 -05:00
Ross Thompson
a93c5b0f0a
Trade off. Added additional state to bus fsm separating STATE_CACHE_ACCESS into STATE_CACHE_FETCH and STATE_CACHE_EVICT. This allows removing CacheRWDelay. Saves a bit of logic but fsm is more complex. Also the fsm outputs are simplier.
2022-08-31 10:36:30 -05:00
Ross Thompson
ed2a9225ea
Removed unused old versions of the bus controllers.
2022-08-31 09:51:54 -05:00
Ross Thompson
89f13370e2
Removed old signals.
2022-08-31 09:50:39 -05:00
Ross Thompson
5409501ca6
Maybe fixed it?
2022-08-30 18:08:34 -05:00
Ross Thompson
8b9f30c91a
more progress.
2022-08-30 17:32:32 -05:00
Ross Thompson
315f662eb9
More progress.
2022-08-30 15:27:19 -05:00
Ross Thompson
637d60b64c
Progress.
2022-08-30 14:17:00 -05:00
Ross Thompson
8cf3c7b352
new cache bus fsm not working but lints.
...
Forgot a few files in the last commit.
2022-08-30 10:58:07 -05:00
David Harris
5f37e16b62
Fixed rv32e LSU and IFU issues
2022-08-25 20:02:38 -07:00
David Harris
bc0c7d0cd8
Cleaned up SelBusWord
2022-08-25 11:18:13 -07:00
David Harris
3ba961d1a8
renamed BusBuffer to FetchBuffer
2022-08-25 10:44:39 -07:00
Ross Thompson
701324eeb8
Updated ila signals.
...
Improve fpga wave config.
added back in the fpga preload.
2022-08-25 09:03:29 -05:00
Ross Thompson
ebe4339953
Updated fpga test bench.
...
Solved read delay cache bug. Introduced during cache optimizations.
2022-08-21 15:59:54 -05:00
Ross Thompson
85dbec5969
Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation.
2022-08-21 15:28:29 -05:00
Ross Thompson
2ba390adf4
Possible reduction of ignorerequest.
2022-08-19 18:07:44 -05:00
Ross Thompson
517c0f6c35
Changed signal names.
2022-08-17 16:12:04 -05:00
Ross Thompson
f6e5746e59
Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.
2022-08-17 16:09:20 -05:00
Ross Thompson
413a9bf58b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-01 22:09:11 -05:00
Ross Thompson
57fcf0ef79
Fixed fstore2 in cache?
2022-08-01 22:04:44 -05:00
Ross Thompson
3cd8404917
Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.
2022-08-01 21:08:14 -05:00
Katherine Parry
1bd6351e1f
re-added FStore2 in Cache
2022-07-29 22:54:49 +00:00
Ross Thompson
40e7cda84a
Don't use this commit yet. Untested.
2022-07-24 15:40:52 -05:00
Ross Thompson
719b00e338
Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.
2022-07-24 01:20:29 -05:00
Ross Thompson
69d520a7eb
Removed replay from the config files.
2022-07-24 00:34:11 -05:00
Ross Thompson
cd68896637
Merged evict dirty clear with flush write back.
2022-07-24 00:22:43 -05:00
Ross Thompson
05484c4c05
signal name cleanup.
2022-07-22 23:36:27 -05:00
Ross Thompson
27e32980ad
cache cleanup after removing replay on cpubusy.
2022-07-22 23:30:25 -05:00
Ross Thompson
17ae1a1b1b
cache fsm cleanup after removal of replay.
2022-07-22 23:25:09 -05:00
Ross Thompson
abc79c6c8e
Possible improvement to cache which removes the cpu_busy states.
2022-07-22 23:20:37 -05:00
Ross Thompson
1cad05fef9
Minor cleanup of cache.
2022-07-19 23:04:23 -05:00
Ross Thompson
8698799077
Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.
2022-07-19 22:42:25 -05:00
Ross Thompson
a79e5e11f6
Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.
2022-07-18 23:37:18 -05:00
Ross Thompson
0ef6137ab9
Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.
2022-07-17 21:05:31 -05:00
Ross Thompson
8356e5d742
Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.
2022-07-17 16:20:04 -05:00
Katherine Parry
18d7fee541
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
2022-07-12 22:37:20 +00:00
David Harris
03a20610aa
added comment about checking SRAM size
2022-07-10 12:48:51 +00:00
David Harris
d1a7832dd9
added comment about RAMs in cacheway
2022-07-10 12:47:34 +00:00
Katherine Parry
62205ebb3b
renamed FLoad2 to FStore2
2022-07-09 00:26:45 +00:00
Katherine Parry
97e7e619d9
moved fpu ieu write data mux to lsu
2022-07-08 23:56:57 +00:00
James Stine
99fed5d59f
Update SRAM to /proj/wally
2022-07-08 08:09:55 -05:00
David Harris
38ef8eebbb
Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables
2022-07-08 08:44:37 +00:00
David Harris
425fec0f41
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
2022-07-07 22:00:59 +00:00
Katherine Parry
c581fba4aa
modified wally shared
2022-07-07 21:59:43 +00:00
David Harris
f865994ba1
fixing port errors
2022-07-07 21:57:10 +00:00
Katherine Parry
7771f7b3eb
added load and store test
2022-07-07 21:48:51 +00:00
David Harris
f2915129ab
Preliminary SRAM integration
2022-07-07 19:56:20 +00:00
Ross Thompson
d716c25275
Fixed an issue with direct map cache's nextway logic.
...
Also found a small error in the replacement policy.
2022-07-06 18:34:30 -05:00
Madeleine Masser-Frye
d8ea12c6f4
fixed concatenation syntax
2022-07-05 22:36:54 +00:00
Katherine Parry
8f98f3bfab
added rv32 double precision stores - untested
2022-06-28 21:33:31 +00:00
David Harris
8372bc86a7
Removing unused signals
2022-05-12 14:36:15 +00:00
David Harris
cb1a7d54a4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-05-03 08:53:35 -07:00
David Harris
4fbf78e049
clean up sram1p1rw; still doesn't work on Modelsim 2022.1
2022-05-03 08:31:54 -07:00
David Harris
7e3f75a35d
Formatting cache.sv
2022-05-03 10:53:20 +00:00
David Harris
bc132c3e20
sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera
2022-05-03 03:50:41 -07:00
David Harris
3f2ec0499f
Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense.
2022-05-03 03:45:41 -07:00
Ross Thompson
ab9738d3be
Hacky fix to prevent ITLBMissF and TrapM bug.
2022-04-12 17:56:23 -05:00
Ross Thompson
b2a77da96b
Changed sram1p1rw to have the same type of bytewrite enables as bram.
2022-03-30 11:38:25 -05:00
Ross Thompson
3dbf6790e1
Towards allowing dtim + bus.
2022-03-11 14:58:21 -06:00
Ross Thompson
81a2fbb6d2
mild cleanup.
2022-03-11 13:05:47 -06:00
Ross Thompson
11e5aad38a
Moved subcachelineread inside the cache. There is some ugliness to still resolve.
2022-03-11 12:44:04 -06:00
Ross Thompson
a12016e69b
Moved subcacheline read inside the cache.
2022-03-11 11:03:36 -06:00
Ross Thompson
326ecda060
removed unused parameter.
2022-03-11 10:43:54 -06:00
Ross Thompson
bdfca503fa
Name cleanup.
2022-03-10 18:44:50 -06:00
Ross Thompson
d77adbd673
Signal name cleanup.
2022-03-10 18:26:58 -06:00
Ross Thompson
83133f8c47
Partially working byte write enables. Works for cache, but not dtim or bus only.
2022-03-10 16:11:39 -06:00
Ross Thompson
d5f524a15e
Added byte write enables to cache SRAMs.
2022-03-10 15:48:31 -06:00
Ross Thompson
60e6c1ffa7
Moved cacheable signal into cache.
2022-03-08 16:34:02 -06:00
David Harris
48705457d5
LSU/Cache code review notes
2022-03-04 00:07:31 +00:00
Ross Thompson
fcbb577f31
Cache mods to be consistant with diagrams.
2022-02-14 12:40:51 -06:00
Ross Thompson
6e1a0af5d0
Eliminated more ports in cacheway.
2022-02-13 15:53:46 -06:00
Ross Thompson
a440bc2ac5
More cache cleanup.
2022-02-13 15:47:27 -06:00
