Ross Thompson 85dbec5969 Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation.		2022-08-21 15:28:29 -05:00
..
cache.sv	Possible reduction of ignorerequest.	2022-08-19 18:07:44 -05:00
cachefsm.sv	Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation.	2022-08-21 15:28:29 -05:00
cachereplacementpolicy.sv	Fixed an issue with direct map cache's nextway logic.	2022-07-06 18:34:30 -05:00
cacheway.sv	Fixed fstore2 in cache?	2022-08-01 22:04:44 -05:00
sram1p1rw.sv	Possible improvement to cache which removes the cpu_busy states.	2022-07-22 23:20:37 -05:00
subcachelineread.sv	Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.	2022-08-01 21:08:14 -05:00
ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v	Update SRAM to /proj/wally	2022-07-08 08:09:55 -05:00