cvw/pipelined/src/cache
2022-09-13 17:51:55 -05:00
..
cache.sv Optimization. Able to remove hptw address muxes from the E stage. 2022-09-08 15:51:18 -05:00
cachefsm.sv pipelining of fetch into evict AHB requests. 2022-09-13 17:51:55 -05:00
cachereplacementpolicy.sv Fixed an issue with direct map cache's nextway logic. 2022-07-06 18:34:30 -05:00
cacheway.sv Fixed fstore2 in cache? 2022-08-01 22:04:44 -05:00
sram1p1rw.sv Updated ila signals. 2022-08-25 09:03:29 -05:00
subcachelineread.sv Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask. 2022-08-01 21:08:14 -05:00
ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v Update SRAM to /proj/wally 2022-07-08 08:09:55 -05:00