Commit Graph

7315 Commits

Author SHA1 Message Date
David Harris
b67b1f5719 Merge pull request #471 from stineje/main
Fix multitude of issues with plotPPA as well as issue related to Popen issuing too many synthesis
2023-11-14 05:51:20 -08:00
James E. Stine
9dce08a743 minor typo on ppaSynth and ppaAnalyze 2023-11-14 02:41:44 -06:00
James E. Stine
c722e2c59d fix plotPPA and other excruciatingly painful problems related to using allWidths and causing empty arrays to be used. This generates the normalized/unnormalized plots 2023-11-14 01:06:14 -06:00
James E. Stine
6374d1a200 Modify ppaSynth.py to be able to not issue excess number of operations with Pool command. This is due to the original command using the Popen command, whereas, using the subprocess.call command solves this issue. The relieves the python script from issuing a ton of synthesis commands and using up all the licenses 2023-11-14 01:04:37 -06:00
David Harris
18dddb85b5 Merge pull request #470 from stineje/main
Remove ppa_ prefix and modify ppaAnalyze.py to handle correct vector
2023-11-13 11:25:38 -08:00
James E. Stine
74056246d4 Remove ppa_ prefix and modify ppaAnalyze.py to handle correct vector 2023-11-13 10:02:10 -06:00
David Harris
62ab604113 Merge pull request #469 from stineje/main
update ppaAnalyze to analyze correctionly freqSweep
2023-11-13 05:33:37 -08:00
James E. Stine
46bfdf5df9 update ppaAnalyze to analyze correctionly freqSweep 2023-11-13 02:39:25 -06:00
Rose Thompson
8235f66af8 Merge pull request #468 from davidharrishmc/dev
Divider optimization
2023-11-12 20:05:44 -08:00
David Harris
571c7d3be4 Divider cleanup 2023-11-12 19:41:12 -08:00
David Harris
f437336540 Explained sqrt preshifting 2023-11-12 10:05:54 -08:00
David Harris
7c50b2c571 Renamed qsel to uslc and simplified radix2 uslc 2023-11-12 06:36:57 -08:00
David Harris
002034845a fdivsqrt comment improvements 2023-11-12 06:15:47 -08:00
Rose Thompson
4c2a9c7bab Merge pull request #467 from davidharrishmc/main
Sanity in FDIVSQRT bit counts
2023-11-11 16:37:25 -08:00
David Harris
6ac83c776e Cleaned up number of bits in fdivsqrt 2023-11-11 15:50:06 -08:00
David Harris
2bf5143163 Bug fixes related to size of fpdivsqrt bit count and number of cycles 2023-11-11 05:58:53 -08:00
David Harris
448ced00c5 Fixed testbench-fp to reflect signal name changes 2023-11-11 04:05:34 -08:00
Rose Thompson
0d6fb879aa Merge pull request #466 from stineje/main
Add pap runs for sweep
2023-11-10 22:25:55 -08:00
Rose Thompson
3af8e1ff50 Merge pull request #465 from davidharrishmc/dev
fdivsqrt cleanup
2023-11-10 22:25:09 -08:00
James E. Stine
7b79d8edeb Update scripts/synth.tcl to add with parameter for width and also checks wrapper to see if running CONFIG=rv32e to run without WIDTH 2023-11-10 21:10:35 -06:00
James E. Stine
65e536e401 Update ppa/ppaSynth.py for sky130 and better sweep parameterization 2023-11-10 21:07:36 -06:00
James E. Stine
e1c935bd9b Add bestSynths.csv that are the initial values. If this is re-run after ppaAnalysis.py is run, more refinement can be made 2023-11-10 21:06:24 -06:00
James E. Stine
91d7790251 update README for ppaSynth.py 2023-11-10 21:05:42 -06:00
David Harris
d5ba8fc5e6 fdivsqrt parameter cleanup 2023-11-10 18:33:08 -08:00
David Harris
3cae2385ab Simplified out LOGRK parameter 2023-11-10 18:19:41 -08:00
David Harris
7d0d9dcebe divider cleanup 2023-11-10 18:01:13 -08:00
David Harris
03864642a7 fdivsqrt cleanup 2023-11-10 16:42:32 -08:00
David Harris
c5b12b7331 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-10 16:40:54 -08:00
David Harris
3108b58290 Simplified integer postnormalization shift 2023-11-10 14:55:36 -08:00
David Harris
b315ead575 Simplified IntDivNormShift 2023-11-10 14:28:57 -08:00
David Harris
2903791820 Simplified cycle count logic 2023-11-10 14:00:27 -08:00
David Harris
8f87860146 Reduced duplicated logic in fdivsqrtcycles 2023-11-10 11:25:54 -08:00
David Harris
255873a50c Divsqrt cleanup: change Q to U, commenting code 2023-11-10 11:21:02 -08:00
David Harris
953c53d065 fdivsqrt parameter cleanup 2023-11-10 09:11:15 -08:00
Rose Thompson
e1a7c7986a Merge pull request #463 from davidharrishmc/dev
Dev
2023-11-10 08:48:07 -08:00
David Harris
4c106215f4 Started cleaning up shifting leading 1 in fdivsqrt 2023-11-10 08:46:55 -08:00
David Harris
426aabbc1a Imperas commenting 2023-11-10 08:26:32 -08:00
David Harris
7e00581187 Add Svadu support and SPI to imperas configuration 2023-11-10 06:27:25 -08:00
David Harris
d7ced56c60 Merge pull request #460 from naichewa/main
removed vestigial logic, added comments, deleted unused signals
2023-11-10 05:18:57 -08:00
naichewa
5ce16dcb63 Cleanup 2023-11-09 16:52:55 -08:00
naichewa
3052a68d84 Remove old 2/4 bit logic, add comments,
clean up unused signals
2023-11-09 16:48:11 -08:00
David Harris
bae3772548 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-09 10:33:25 -08:00
Rose Thompson
1d2eccc14d Merge pull request #458 from stineje/main
fix to setup.csh and also ppaSynth.py
2023-11-09 10:20:05 -08:00
David Harris
625652b9ca Reporting stall path in synthesis script, support Zcb in Imperas 2023-11-09 06:59:29 -08:00
James E. Stine
9a47667fd7 update README on ppa 2023-11-09 01:00:33 -06:00
James E. Stine
5a115bc6f2 update ppaSynth.py with runCommand 2023-11-09 00:52:40 -06:00
James E. Stine
a6bc69d73f Add encoding for utf-8 on wrapperGen.py to avoid issue with incorrect encoding on RHEL C-shell 2023-11-08 23:57:59 -06:00
David Harris
32f68ac4e5 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-08 16:06:50 -08:00
David Harris
0e1b4bf8f6 Merge pull request #459 from naichewa/main
hardware interlock and hold mode fixes
2023-11-08 16:06:39 -08:00
naichewa
b13b8feee4 updated to-do comments 2023-11-08 15:28:51 -08:00