slmnemo
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87cfd62e19
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Added line to testbench to prevent annoying burst sizes
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2022-05-25 17:29:45 -07:00 |
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DTowersM
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41f6233a70
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-26 00:12:46 +00:00 |
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slmnemo
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5a9e3a852a
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see commit 9042cc3c
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2022-05-25 17:10:59 -07:00 |
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DTowersM
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aa574d545c
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Merge branch 'embench' into main
embench contained the working makefiles for embench and is being merged into main as it working and done
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2022-05-26 00:10:50 +00:00 |
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DTowersM
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5e87506772
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working makefile for embench and removed testbench-f64
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2022-05-26 00:08:18 +00:00 |
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slmnemo
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d43d340e31
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added logic to prevent cache line length from exceeding the max size of a burst.
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2022-05-25 17:03:15 -07:00 |
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Katherine Parry
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c264585fe8
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single and double conversions pass all tests
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2022-05-25 23:02:02 +00:00 |
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slmnemo
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a5d5bd272b
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changes suggested by ben, hopefully fixing buildroot (which is now not running)
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2022-05-20 18:42:38 -07:00 |
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Katherine Parry
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6bc31f2e78
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Fixed unpacker bug LT EQ LE pass testfloat
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2022-05-20 17:19:50 +00:00 |
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slmnemo
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6c237e43d8
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-05-19 17:51:45 -07:00 |
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slmnemo
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0982417054
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Fixed buildroot by adding a second .
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2022-05-19 17:49:32 -07:00 |
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slmnemo
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7d2bfb6db8
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parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do
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2022-05-19 16:21:38 -07:00 |
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Katherine Parry
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b0881495a9
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Bug fixed in unpacker and sub/add/mul tests pass TestFloat
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2022-05-19 20:31:23 +00:00 |
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Katherine Parry
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cc0ab94ebc
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Added fp tests - doesnpass yet
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2022-05-19 16:32:30 +00:00 |
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slmnemo
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ba572b46f4
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Updated testbench to initialize using force and releases storing zero in all memory locations in branch predictor. Fixed arch64i bug related to failing bge due to an incorrect signature.
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2022-05-17 01:04:13 +00:00 |
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slmnemo
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ede0a3237d
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quit
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2022-05-17 01:03:09 +00:00 |
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David Harris
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730bcac6ba
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Partitioned privileged pipeline registers into module
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2022-05-12 20:45:45 +00:00 |
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David Harris
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21c1e58829
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Partitioned privilege mode fsm into new module
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2022-05-12 16:16:42 +00:00 |
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David Harris
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e2dea3bb89
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Removed more unused signals, simplified csri state
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2022-05-12 15:10:10 +00:00 |
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mmasserfrye
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52b0e7d567
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filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv
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2022-05-12 07:22:06 +00:00 |
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David Harris
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a8c9f504fa
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Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt
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2022-05-11 15:08:33 +00:00 |
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David Harris
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91472eb948
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Removed M suffix from interrupts because they are generated asynchronously to pipeline
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2022-05-11 14:41:55 +00:00 |
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David Harris
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66424a8246
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SFENCE.VMA should be illegal in user mode
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2022-05-05 15:15:02 +00:00 |
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David Harris
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c100c9893b
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wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts
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2022-05-05 14:37:21 +00:00 |
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David Harris
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94459ade3d
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Changed WFI to stall pipeline in memory stage
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2022-05-05 02:03:44 +00:00 |
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Kip Macsai-Goren
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0f70e48b6b
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updated makefrag and tests.vh to reflect removed tests, new names
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2022-05-04 21:20:25 +00:00 |
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Kip Macsai-Goren
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e557e420b6
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added missing SIE test
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2022-04-29 19:54:29 +00:00 |
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Kip Macsai-Goren
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5df381e26f
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renamed PIE-stack tests to status-mie for clarity
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2022-04-29 18:30:39 +00:00 |
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Kip Macsai-Goren
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c3ffcd0e95
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removed old unused tests from wally arch tests
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2022-04-28 18:14:08 +00:00 |
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Kip Macsai-Goren
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0e5cc40360
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added 32 bit versions of new tests. all but timeout wait pass regression
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2022-04-28 18:14:07 +00:00 |
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Skylar Litz
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970f6c4222
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-27 10:50:19 -07:00 |
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Skylar Litz
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594db170de
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fix AttemptedInstructionCount from ground zero
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2022-04-27 10:45:40 -07:00 |
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Kip Macsai-Goren
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0f4ca62157
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added working tests to test list, updated regression for new configs
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2022-04-25 19:18:15 +00:00 |
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Kip Macsai-Goren
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7ff85258f0
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added new tests to tests.vh, comented out until they pass regression
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2022-04-25 18:22:44 +00:00 |
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David Harris
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0ede295e88
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Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields
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2022-04-25 14:49:00 +00:00 |
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Ross Thompson
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8fcd4d47b7
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-21 09:52:42 -05:00 |
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Kip Macsai-Goren
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cd53163d9a
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added new tests to tests.vh
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2022-04-20 17:34:40 +00:00 |
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Kip Macsai-Goren
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510021af65
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added working general trap tests to regression
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2022-04-20 06:48:01 +00:00 |
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Ross Thompson
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546ef08eb2
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-19 14:09:50 -05:00 |
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Kip Macsai-Goren
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64698aa806
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Added working trap test to regression, fixed hanfling of some interrupts
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2022-04-18 07:22:16 +00:00 |
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Ross Thompson
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a99466a487
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Fixed bug I introduced by csrc cleanup and changes to ILA.
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2022-04-17 21:45:46 -05:00 |
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Ross Thompson
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c409bde6ae
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fixed no forcing bug in linux testbench.
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2022-04-17 17:49:51 -05:00 |
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David Harris
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de5b61291f
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Experiments with prefix comparator; minor fixes in WFI and testbench warnings
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2022-04-17 21:43:12 +00:00 |
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Kip Macsai-Goren
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1f9c987efe
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added new tests to makefrag and tests.vh
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2022-04-17 21:00:36 +00:00 |
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David Harris
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a28831b83e
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Added WFI to the testbench instruction name decoder
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2022-04-14 17:12:11 +00:00 |
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bbracker
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fe53dd1683
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fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM
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2022-04-14 09:23:21 -07:00 |
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bbracker
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eb21e34000
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fix ReadDataM forcing
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2022-04-13 15:32:00 -07:00 |
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Ross Thompson
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2e8afd071e
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-13 13:39:47 -05:00 |
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bbracker
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735c75af55
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change interrupt spoofing to happen at negative clock edges
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2022-04-13 04:31:23 -07:00 |
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bbracker
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52ed99ca1b
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improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS
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2022-04-13 03:37:53 -07:00 |
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bbracker
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03f1c01f14
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whoops forgot to update AttemptedInstructionCount in interrupt spoofing
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2022-04-13 00:49:37 -07:00 |
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bbracker
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d3e9703c19
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change testbench-linux to by default use attempted instruction count for warning/error messages
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2022-04-12 21:22:08 -07:00 |
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Ross Thompson
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fc173a7954
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Missed the force on uart for no tracking.
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2022-04-12 19:37:44 -05:00 |
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Ross Thompson
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f995ec2a54
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-10 13:41:27 -05:00 |
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Ross Thompson
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c3d9eafe60
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Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing.
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2022-04-10 13:27:54 -05:00 |
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bbracker
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aa71fe542d
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upgrade testbench interrupt forcing such that first m_timer interrupt now successfully spoofs
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2022-04-08 13:45:27 -07:00 |
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bbracker
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3b6cb5f0ba
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small signs of life on new interrupt spoofing
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2022-04-08 12:32:30 -07:00 |
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Ross Thompson
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5e4682fb65
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Fixed typo in tests.vh
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2022-04-07 16:28:28 -05:00 |
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Kip Macsai-Goren
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7425c49f58
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updated test signature locations
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2022-04-06 07:28:38 +00:00 |
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Katherine Parry
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20885f4dea
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generating all testfloat vectors
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2022-04-04 17:17:12 +00:00 |
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Ross Thompson
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57eba4355e
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Updated the fpga test bench.
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2022-04-01 17:14:47 -05:00 |
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bbracker
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54b9745a75
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big interrupts refactor
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2022-03-30 13:22:41 -07:00 |
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Ross Thompson
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3ac736e2d5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-30 11:09:44 -05:00 |
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Ross Thompson
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1993069986
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Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.
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2022-03-30 11:04:15 -05:00 |
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Ross Thompson
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fc2b4453ec
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rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.
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2022-03-29 23:48:19 -05:00 |
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Ross Thompson
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de2672231d
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Partial fix to allow byte write enables with fpga and still get a preload to work.
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2022-03-29 19:12:29 -05:00 |
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Kip Macsai-Goren
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b252122d62
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fixed arch bge test signature output location after update
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2022-03-29 20:45:18 +00:00 |
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Kip Macsai-Goren
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c32f5e9cee
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fixed signature location of the new periph with no compressed instructions
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2022-03-29 02:15:17 +00:00 |
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Skylar Litz
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29d1f64588
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add AtemptedInstructionCount signal
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2022-03-26 21:28:57 +00:00 |
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Kip Macsai-Goren
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8cde06b886
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added basic trap tests that do not pass regression yet. updated signature adresses
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2022-03-25 22:57:41 +00:00 |
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bbracker
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b08066381a
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fix multiple-context PLIC checkpoint generation
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2022-03-25 01:02:22 +00:00 |
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bbracker
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150a7b234b
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tabs vs spaces disagreement
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2022-03-24 17:11:41 -07:00 |
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bbracker
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9f60256f22
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1st attempt at multiple channel PLIC
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2022-03-24 17:08:10 -07:00 |
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Ross Thompson
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58668812c1
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Moved WriteDataM register into LSU.
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2022-03-23 14:17:59 -05:00 |
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Ross Thompson
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f1787670d4
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Cleanup in testbench-linux.sv.
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2022-03-22 22:34:38 -05:00 |
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Ross Thompson
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c5be2cb1d5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-22 21:28:50 -05:00 |
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Ross Thompson
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7fc128ba7c
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added SIP, SIE, and SSTATUS to checkpoints. Can't seem to get the linux testbench to force SIP.
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2022-03-22 21:28:34 -05:00 |
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Ross Thompson
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80d376877a
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Added spoof of uart addresses +0x2 and +0x6.
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2022-03-22 16:52:27 -05:00 |
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Katherine Parry
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2042374102
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FMA parameterized and FMA testbench reworked
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2022-03-19 19:39:03 +00:00 |
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Ross Thompson
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d68446cf92
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Added new asserts to testbench.
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2022-03-11 15:41:53 -06:00 |
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bbracker
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51e68819c4
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fix up PLIC and UART checkpointing
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2022-03-07 23:48:47 -08:00 |
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bbracker
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c2ac18b5de
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change testbench-linux.sv to use new shared location of disassembly files
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2022-03-07 20:04:08 -08:00 |
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David Harris
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9fd861a9ee
|
removed more old 64priv tests
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2022-03-04 03:57:19 +00:00 |
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bbracker
|
1c5697874f
|
comment out nonfunctioning CSR-PERMISSIONS-M test
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2022-03-04 00:11:55 +00:00 |
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bbracker
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443dd40ea8
|
remove imperas32p tests
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2022-03-04 00:06:18 +00:00 |
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bbracker
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e28ca531e0
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fix peripheral test and add it to regression
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2022-03-02 23:44:39 +00:00 |
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bbracker
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d7b8c9d877
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add rv32a tests to regression
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2022-03-02 17:54:55 +00:00 |
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bbracker
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5f5cc514b8
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fix buildroot checkpointing and add it back to regression
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2022-03-02 16:00:19 +00:00 |
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bbracker
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4f22a55dd4
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add LRSC test and add wally64a to regression
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2022-03-02 07:09:37 +00:00 |
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bbracker
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04ace8c154
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switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv
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2022-03-01 03:11:43 +00:00 |
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bbracker
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d620fb4442
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deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test
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2022-03-01 00:37:46 +00:00 |
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David Harris
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f314e60dc8
|
Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath
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2022-02-28 20:50:51 +00:00 |
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bbracker
|
a6047697c3
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-02-22 04:27:50 +00:00 |
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bbracker
|
6caa97bb26
|
change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
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2022-02-22 03:46:08 +00:00 |
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Kip Macsai-Goren
|
d1578d8356
|
added scratch register tests for 64 and 32 bits
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2022-02-21 07:03:12 +00:00 |
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Kip Macsai-Goren
|
4113d64b19
|
added 32 bit pma tests to regression even though they've been working fo a while
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2022-02-18 19:43:24 +00:00 |
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Kip Macsai-Goren
|
c3523dfa15
|
Added misa test for both 32 and 64 bits
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2022-02-18 19:41:50 +00:00 |
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Kip Macsai-Goren
|
6c1383e2a0
|
added CSR permission and minfor to 32 bit tests
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2022-02-15 20:19:14 +00:00 |
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Kip Macsai-Goren
|
5df0a9531f
|
merged test macros in with 32 bit tests
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2022-02-15 20:19:14 +00:00 |
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David Harris
|
ed8ac3d881
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Just needed to recompile - all good. Now removed uretM because N-mode is depricated
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2022-02-15 19:48:49 +00:00 |
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