Ross Thompson c3d9eafe60 Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing.		2022-04-10 13:27:54 -05:00
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common	Just needed to recompile - all good. Now removed uretM because N-mode is depricated	2022-02-15 19:48:49 +00:00
fp	generating all testfloat vectors	2022-04-04 17:17:12 +00:00
sdc
testbench-coremark_bare.sv
testbench-f64.sv	Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath	2022-02-28 20:50:51 +00:00
testbench-fpga.sv	Updated the fpga test bench.	2022-04-01 17:14:47 -05:00
testbench-linux.sv	Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing.	2022-04-10 13:27:54 -05:00
testbench.sv	Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.	2022-03-30 11:04:15 -05:00
tests.vh	Fixed typo in tests.vh	2022-04-07 16:28:28 -05:00