Jarred Allen
c0ee17b6ac
Merge upstream changes
2021-03-09 21:20:34 -05:00
David Harris
0baa004bb4
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-09 09:28:32 -05:00
David Harris
bea8ac6d59
WALLY-LRSC atomic test passing
2021-03-09 09:28:25 -05:00
Noah Boorstin
9274d09ae2
busybear: better instrF checking
...
So this now checks instrF only when StallD is low. @kaveh I'd love your
opinion on this. I don't know if this is a good idea or not. Ideally we
should probably be checking InstrRawD instead, but I kind of want to stay
checking the instr in the F stage instead of D for now. Idk if this is worth
staying in F, I can't really see any big downsides to checking the instruction in
D except that PCD isn't an external signal, but neither is StallD, so.....
Anyway I'd love others' thoughts on this
2021-03-08 19:48:12 +00:00
Noah Boorstin
08e3691e59
busybear: make a second .do file with better optimization for command line mode
2021-03-08 19:35:00 +00:00
Noah Boorstin
1fc00d41c2
busybear: load mem files from verilog instead of .do
2021-03-08 19:26:26 +00:00
Ross Thompson
a3759f585d
Updated the paths to the branch predictor memory preloads for busy bear.
2021-03-05 15:36:00 -06:00
Ross Thompson
d6bc34121f
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-05 15:27:22 -06:00
Ross Thompson
9a93193d6a
Oups. I forgot to update other do files with the commands to preload the branch predictor memories.
2021-03-05 15:23:53 -06:00
Noah Boorstin
d3bf36b15f
busybear: add branch preditor loading to do file
...
(sorry to add more loading to the do instead of less)
2021-03-05 21:01:41 +00:00
Noah Boorstin
f0a103687e
Merge branch 'main' into busybear
2021-03-05 20:27:19 +00:00
Noah Boorstin
6981907521
fix wally-pipelined-batch.do to match wally-pipelined.do
2021-03-05 20:27:01 +00:00
bbracker
420c9a11c2
refactored sim file
2021-03-05 14:25:16 -05:00
bbracker
62dd9e3075
first merge of ahb fix
2021-03-05 14:24:22 -05:00
Noah Boorstin
7208b9bcf2
busybear: better implenetation of sim-busybear-batch
2021-03-05 00:39:03 +00:00
Noah Boorstin
cfcd7d1518
busybear: make imperas tests work again
2021-03-04 22:44:49 +00:00
Jarred Allen
b0f4d8e8d4
Remove rd2, working for non-compressed
2021-03-04 16:46:43 -05:00
Noah Boorstin
fde94f9057
Merge branch 'main' into busybear
...
Conflicts:
wally-pipelined/src/uncore/imem.sv
2021-03-04 20:16:03 +00:00
Ross Thompson
619bbd9d83
Merge branch 'bp' into main
...
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
Teo Ene
b50faef94d
Updated coremark .do file for easier debugging
2021-03-03 15:10:39 -06:00
Teo Ene
d02e22feac
Updated coremark .do file for easier debugging
2021-03-02 17:23:39 -06:00
Noah Boorstin
beb2beabfd
busybear: add sim-busybear and sim-busybear-batch based on sim-wally
2021-03-01 21:01:15 +00:00
Noah Boorstin
923489fe16
busybear: probably discovered bug in ahb code
2021-03-01 20:56:04 +00:00
Noah Boorstin
b3247eadd2
busybear: more adapting to new memory system
2021-03-01 18:50:42 +00:00
Noah Boorstin
f11b3108d8
busybear: fix bootram range
2021-03-01 17:45:21 +00:00
Noah Boorstin
a267115635
Merge branch 'main' into busybear
2021-02-28 20:45:08 +00:00
Noah Boorstin
17715085ba
busybear: start preloading bootmem
2021-02-28 20:43:57 +00:00
Noah Boorstin
932bc0ef85
busybear: check instead of providing InstrF
2021-02-28 16:46:53 +00:00
Ross Thompson
6191fcb1af
Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
2021-02-26 20:12:27 -06:00
Ross Thompson
c2cf3f9fb6
Updating the test bench to include a function radix. Not done.
2021-02-26 19:43:40 -06:00
David Harris
73920282af
Eliminated flushing pipeline on CSR reads
2021-02-26 17:00:07 -05:00
kaveh pezeshki
e8b306bcba
merged with main to integrate with AHB
2021-02-26 05:37:10 -08:00
Noah Boorstin
4c7b185d90
busybear: add main ram loading, better instr checking also
2021-02-26 20:26:54 +00:00
Teo Ene
8491deb1a9
Changed .do file back to run all
2021-02-25 09:58:54 -06:00
David Harris
cd4ba8831c
Merged bus into main
2021-02-25 00:28:41 -05:00
Teo Ene
cfd45a46c3
Added provisional coremark files from work with Elizabeth
2021-02-24 20:07:07 -06:00
Noah Boorstin
ddaf67c043
busybear: preload bootram
...
thanks to Prof Stine for the .do file commands
@kaveh can you check line 201? it does nothing, but things break when
I remove that line
2021-02-24 18:46:09 +00:00
Noah Boorstin
7b7e87bd0b
busybear: start adding ram
2021-02-23 22:01:23 +00:00
Noah Boorstin
c42c485377
busybear: instantiate soc instead of hart
2021-02-23 18:59:06 +00:00
kaveh pezeshki
e146946e58
Merge remote-tracking branch 'origin/tlb_toy' into busybear
2021-02-22 02:23:01 -08:00
Ross Thompson
c856003f73
RAS needs to be reset or preloaded. For now I just reset it.
...
Fixed bug with the instruction class.
Most tests now pass. Only Wally-JAL and the compressed instruction tests fail. Currently the bpred does not support compressed. This will be in the next version.
2021-02-19 20:09:07 -06:00
Ross Thompson
597dd1e7e6
Added FlushF to hazard unit.
...
Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
2021-02-19 16:36:51 -06:00
Ross Thompson
06e975ac2f
minor change to wave file.
2021-02-19 09:08:13 -06:00
Ross Thompson
7d6093b302
Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary.
...
About 149307ns of simulation run.
2021-02-18 21:32:15 -06:00
Ross Thompson
8cbc9f7e51
Wrote a bash script to generate custom modelsim radix which maps instruction addresses into human readable lables.
...
Once combined with some simulation verilog this will display the current function in modelsim.
2021-02-17 22:20:28 -06:00
Ross Thompson
bbe0db3ebe
Integrated the branch predictor into the hardward. Not yet working.
2021-02-17 22:19:17 -06:00
Noah Boorstin
84d856d1e5
busybear: allow testbench to ignore lack of MMU for now
...
I'd really like to go over this with someone else, not sure if this is
a good thing to be doing
If it is, we're at 1M instructions!
2021-02-12 20:08:56 +00:00
bbracker
deb7780897
bus rw bugfix and peripherals testing
2021-02-12 00:02:45 -05:00
Teo Ene
5f84ed407c
Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts
2021-02-10 20:48:39 -06:00
David Harris
842c374de9
Debugging instruction fetch
2021-02-09 11:02:17 -05:00
