Sydney Riley
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20fec0177d
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Corrected authorship for IFU.S tests file
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2023-03-29 15:20:46 -07:00 |
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Sydney Riley
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b0237eaa8b
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Starting IFU tests including c.fld compressed instruction
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2023-03-29 15:15:47 -07:00 |
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David Harris
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d059da6eca
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Turned on FS bit in fpu.S coverage test
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2023-03-29 06:10:05 -07:00 |
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Diego Herrera Vicioso
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36d7ddf501
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Added test coverage cases for writing to STVAL, SCAUSE, SEPC, and STIMECMP CSRs.
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2023-03-28 22:48:17 -07:00 |
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David Harris
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3dc1c6673d
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Started adding fpu fctrl tests
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2023-03-28 21:13:25 -07:00 |
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David Harris
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2e5c50e24a
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Fixed RV32 tests after PMP fix
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2023-03-28 08:35:23 -07:00 |
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David Harris
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e8904411ce
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Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests
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2023-03-28 06:58:17 -07:00 |
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David Harris
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4594dffc7f
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Set PMP to allow all user/supervisor accesses in WALLY-init-lib
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2023-03-28 06:46:11 -07:00 |
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David Harris
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2e238c15aa
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CSRS privileged coverage test
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2023-03-28 04:37:56 -07:00 |
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Kip Macsai-Goren
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106ed02a7e
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Revert "added premilinary boundary ccrossing cases"
This reverts commit 7870148814.
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2023-03-24 11:27:41 -07:00 |
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Kip Macsai-Goren
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758da62a9f
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ported fixes to 32 bit tests
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2023-03-24 11:22:39 -07:00 |
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Kip Macsai-Goren
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ff59fefcc9
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replaced inerrupt tests with allowed versions
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2023-03-24 11:22:39 -07:00 |
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Kip Macsai-Goren
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6f15ae1225
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Added cause_s_soft_from_m_interrupt
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2023-03-24 11:22:39 -07:00 |
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Kip Macsai-Goren
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7870148814
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added premilinary boundary ccrossing cases
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2023-03-24 11:22:39 -07:00 |
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David Harris
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f1e87c5e69
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Start of EBU coverage tests
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2023-03-24 08:12:02 -07:00 |
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David Harris
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b674ebf7f4
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100% IEU coverage
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2023-03-23 17:25:27 -07:00 |
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David Harris
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4e1bf6fbe0
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Improved IEU and bitmanip test coverage
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2023-03-23 14:24:41 -07:00 |
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David Harris
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121d1cea62
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Added csrwrites.S test case for privileged tests
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2023-03-23 10:55:32 -07:00 |
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David Harris
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f4b252522e
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Coverage improvements
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2023-03-23 09:06:05 -07:00 |
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David Harris
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ba4e0d2721
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Merged bit manip
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2023-03-23 06:55:29 -07:00 |
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David Harris
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610b50a693
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Added new tests from class
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2023-03-23 06:38:00 -07:00 |
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Kip Macsai-Goren
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c870b16c03
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Merge branch 'bit-manip' of github.com:kipmacsaigoren/cvw into bit-manip
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2023-03-22 14:11:58 -07:00 |
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kipmacsaigoren
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72028ab754
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Merge branch 'openhwgroup:main' into bit-manip
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2023-03-22 13:25:06 -07:00 |
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Kip Macsai-Goren
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44b5e234bd
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Removed unused ISA string from spike YAML
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2023-03-22 13:23:52 -07:00 |
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David Harris
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3b3aa942c7
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Added coverage tests to regression coverage
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2023-03-22 13:00:10 -07:00 |
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David Harris
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31021265b8
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Makefile improvements
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2023-03-22 11:17:17 -07:00 |
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Kevin Kim
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1eb96e2221
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Merge branch 'openhwgroup:main' into bit-manip
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2023-03-22 10:33:15 -07:00 |
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David Harris
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4a1592ccf8
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Building infrastructure for coverage directed tests
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2023-03-22 04:37:13 -07:00 |
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Kevin Kim
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3f46dff23e
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Merge branch 'main' of https://github.com/openhwgroup/cvw into bit-manip
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2023-03-21 11:20:05 -07:00 |
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David Harris
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18cc620e7f
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Added badinstr test file
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2023-03-21 06:57:03 -07:00 |
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kipmacsaigoren
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2337e2ae16
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Merge branch 'openhwgroup:main' into bit-manip
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2023-03-07 21:29:03 -08:00 |
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Kip Macsai-Goren
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db6caedfec
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added in the CSR name for stimecmp(h)
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2023-03-04 15:53:03 -08:00 |
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Kip Macsai-Goren
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ab6b953a4b
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removed changes to counteren from stimecmp tests
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2023-03-04 15:46:57 -08:00 |
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Kip Macsai-Goren
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ac5c53a870
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Added correct causing and handling of S time interrupts to test suite.
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2023-03-04 15:04:17 -08:00 |
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Kip Macsai-Goren
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ba3bfdf68b
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Manual attempt to merge with upstream changes
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2023-02-22 19:42:30 -08:00 |
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Kip Macsai-Goren
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0339dc5e78
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added extra commands to make dut run work with spike for bit manip tests
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2023-02-21 15:26:47 -08:00 |
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Kip Macsai-Goren
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d668c563f4
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Merge remote-tracking branch 'upstream/main' into main
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2023-02-21 14:48:41 -08:00 |
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David Harris
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99a1683f8e
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Debug test case updates
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2023-02-21 09:33:36 -08:00 |
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Kip Macsai-Goren
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65a5b86dd8
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Merge remote-tracking branch 'upstream/main' into main
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2023-02-19 16:37:18 -08:00 |
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David Harris
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f0c0111ab0
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Renamed section 12.3 to 8.3 in MMU test definitions
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2023-02-19 05:46:46 -08:00 |
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Kip Macsai-Goren
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9c3aa55349
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merge upstream synth changes
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2023-02-18 14:35:19 -08:00 |
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Kip Macsai-Goren
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ea38e05773
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fixed makefile for 32 bit arch tests, restored original make for all others
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2023-02-17 09:57:56 -08:00 |
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Kip Macsai-Goren
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7344f3ef30
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Modified arch64 tests to remove floating point and double tests from hanging make
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2023-02-17 09:51:55 -08:00 |
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David Harris
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2b80004db4
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Debug test case update
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2023-02-15 06:42:38 -08:00 |
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Kevin Kim
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4fed8d9196
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added critical rsync command to python script and builds I-ext tests
-rsync copies the stuff from riscof_work to work/riscv-arch-test
-
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2023-02-14 10:40:29 -08:00 |
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Kevin Kim
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5fed4c2c87
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updated python script to generate bash file
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2023-02-11 11:08:11 -08:00 |
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Kevin Kim
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7e4fc40dc7
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changed python file to use WALLY env variable
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2023-02-11 00:30:56 +00:00 |
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Kip Macsai-Goren
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76593cb282
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Added necessary files to make bit make and run bit manipulation tests as part of regression
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2023-02-10 10:35:19 -08:00 |
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David Harris
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9a6d7bb16d
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Added RVTEST_CASE to testgen header
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2023-02-09 18:25:24 -08:00 |
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David Harris
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8fb513ad35
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Moved test generators
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2023-02-09 18:24:48 -08:00 |
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David Harris
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edbf962b5f
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Test gen header
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2023-02-09 18:14:26 -08:00 |
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David Harris
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44fef2f2a1
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debug simulating, produing discrepancy
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2023-02-06 16:47:56 -08:00 |
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David Harris
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4c219de13d
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Fixed floating point crash in debug.S
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2023-02-06 15:38:57 -08:00 |
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David Harris
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5256d3a625
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More progress on debug.S, but it crashes in Spike
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2023-02-04 09:59:22 -08:00 |
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David Harris
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43668a3fc5
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Developing debug test
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2023-02-04 08:31:47 -08:00 |
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David Harris
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2c69adc5f7
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Started making debug testcase
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2023-02-04 08:18:55 -08:00 |
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David Harris
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80f42a8638
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Renamed regression to sim
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2023-02-02 14:48:23 -08:00 |
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David Harris
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78eb90715c
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Removed pipelined level of hierarchy
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2023-02-02 14:14:11 -08:00 |
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David Harris
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4883351bd2
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-01-28 18:18:53 -08:00 |
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Kip Macsai-Goren
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ee1bcf62ee
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Fixed regression test dependance on bp status by adding handling of UART tx empty interrupts.
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2023-01-28 17:29:35 -08:00 |
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David Harris
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d8f0e3dd70
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Modified testgen to not produce reference outputs
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2023-01-27 07:25:40 -08:00 |
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David Harris
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cea89f27cf
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Removed unused WALLY test references
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2023-01-27 07:25:04 -08:00 |
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David Harris
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2af94bf283
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Removed unused reference files
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2023-01-27 07:21:55 -08:00 |
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David Harris
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37ba3d0fcd
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Removed f tests from rv32e
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2023-01-27 06:15:20 -08:00 |
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David Harris
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7fbbed7927
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Update riscof makefile to use rv32gc config
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2023-01-27 05:57:58 -08:00 |
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David Harris
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b81b5781e1
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Renamed spike_rv32imc_isa.yaml to rv32gc to reflect cases tested
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2023-01-27 05:56:49 -08:00 |
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David Harris
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7d8a0d9615
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Refactored setup QUESTA and SNPS paths, and removed troublesome bit manipulation test cases
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2023-01-23 05:00:11 -08:00 |
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David Harris
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b173112f86
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Continued framework for B instructions
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2023-01-20 14:27:13 -08:00 |
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Ross Thompson
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97feea2f48
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Possibly working speculative global history.
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2023-01-08 23:46:53 -06:00 |
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Ross Thompson
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a35fb3addd
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core part of global history works now. forwarding is still broken.
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2023-01-08 23:35:02 -06:00 |
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Ross Thompson
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f8c656f1e0
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Simiplified global history branch predictor.
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2023-01-04 23:41:55 -06:00 |
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Kip Macsai-Goren
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964084f0b3
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added fs=00 to status fp enabled test
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2022-12-22 15:15:53 -08:00 |
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Kip Macsai-Goren
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d25d699800
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Added status.tvm bit test that passes make and regression
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2022-12-22 14:43:22 -08:00 |
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Kip Macsai-Goren
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a37bde7452
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updated trap handler alignemnts to 64 bytes in priv tests
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2022-12-22 14:23:04 -08:00 |
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David Harris
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ca949f2110
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Only delegated bits of SIP are readable
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2022-12-21 12:32:49 -08:00 |
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Ross Thompson
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f6393d1288
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Waiting on fix for wally64periph uart test.
would like to remove vectored interrupt adder.
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2022-12-21 13:16:09 -06:00 |
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Ross Thompson
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c41d58bd29
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Vectored interrupts now require 64 byte alignment.
Eliminates adder.
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2022-12-21 12:05:49 -06:00 |
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David Harris
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00ff823d84
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Restored rv32d arch test after new push
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2022-12-20 10:56:33 -08:00 |
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Ross Thompson
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c3b77926d5
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I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl.
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2022-12-18 18:30:35 -06:00 |
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Ross Thompson
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e8c1d14abb
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Have a basic cache test to fill all ways and sets.
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2022-12-18 17:20:30 -06:00 |
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Ross Thompson
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7a352edf13
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Attempted to make a cache test.
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2022-12-18 17:15:08 -06:00 |
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Ross Thompson
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9d1cb9337e
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Updated tests for fpga and BP.
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2022-12-18 16:24:26 -06:00 |
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David Harris
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643a2e7cf9
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Use FPU divider for integer division when F is supported
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2022-12-14 17:03:13 -08:00 |
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Kip Macsai-Goren
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55627f40e2
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added passing GPIO test to 64 bit tests
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2022-12-05 21:31:00 -08:00 |
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Kip Macsai-Goren
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4c81b6fa5f
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added corrrect scr read out of uart to periph test
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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4ab99904a4
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added all 32 bit tests to 64 bit periph tests except gpio
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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51e78d9e48
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added copies of 64 bit tests to 32 bit periph and priv tests
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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540d6c2f41
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added -01 to all WALLY tests
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2022-12-05 20:16:02 -08:00 |
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Ross Thompson
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fc05e27416
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Updated riscv arch test removed misaligned1.
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2022-12-04 00:18:10 +00:00 |
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Kip Macsai-Goren
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9b1765ce92
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added tests for invalid address being written to satp. Not passing regression
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2022-11-27 13:22:35 -08:00 |
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Kip Macsai-Goren
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21e045eb7d
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added potential fix to overrun error and fifo interrupt error. test passes
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2022-11-06 22:01:02 -08:00 |
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Kip Macsai-Goren
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90ef371abc
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fixed fifo timout handling. error now in data ready interrupt
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2022-11-05 13:34:24 -07:00 |
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Kip Macsai-Goren
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c06da6e6fe
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fixed broken instructions so make works.
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2022-11-03 23:06:20 +00:00 |
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Ross Thompson
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f1eb20ef4d
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Updated to put dtb into the rodata segment for our linker script.
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2022-11-03 17:48:20 -05:00 |
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Ross Thompson
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1d7002e5c5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-03 17:36:04 -05:00 |
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Ross Thompson
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ccce0df535
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Potentially a valid zero stage boot loader based on cva6.
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2022-11-03 17:35:57 -05:00 |
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Ross Thompson
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103514a8e0
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More outline for uart timeout interrupt.
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2022-10-28 13:53:56 -05:00 |
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Ross Thompson
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21eca47d2e
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Untested change to uart test for outline of how to handle rx fifo timeout.
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2022-10-28 13:31:16 -05:00 |
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Kip Macsai-Goren
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6e45698b86
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Added test for UART FIFO timeout. Does not pass regression
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2022-10-25 05:35:56 +00:00 |
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Ross Thompson
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a59df0c77d
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Created one off test to replicate the floating point forwarding hazard bug.
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2022-10-22 16:29:12 -05:00 |
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