David Harris
afabc52b61
Gated InstrOrigM and PCMReg when not needed
2023-10-30 20:05:37 -07:00
David Harris
2d17a991d8
rom1p1r code cleanup
2023-10-30 19:47:49 -07:00
David Harris
3f7c67882f
rom1p1r code cleanup
2023-10-30 19:46:38 -07:00
David Harris
90a178e31e
Made 2-bit AdrReg conditional on being needed
2023-10-30 19:13:43 -07:00
David Harris
f6a7f707bd
Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
2023-10-30 09:56:17 -07:00
David Harris
27b8ebb9bd
Fix issue 444 by preventing delegation of misaligned instructions when compressed instructions are supported.
2023-10-30 07:06:34 -07:00
David Harris
734bf021d7
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-10-26 19:02:05 -07:00
Rose Thompson
06b5a92eff
Updated comments about Interrupt and wfi.
2023-10-26 12:24:36 -05:00
Rose Thompson
4cd0584a11
Forgot to include this file in the last commit.
2023-10-26 12:20:42 -05:00
Rose Thompson
3322ff915e
Cleaned up the implementation changes for wfi.
2023-10-24 23:11:48 -05:00
Rose Thompson
c58f04c901
This version passes the regression test and solves issue #200 . wfi's implemenation is changed so that wfi does not take an interrupt in the Memory stage. Instead it advances to the Writeback stage then traps.
2023-10-24 22:58:26 -05:00
Rose Thompson
c61526d034
Possible fix for wfi.
2023-10-24 18:08:33 -05:00
David Harris
3bb7539429
Fixed warnings of signed conversion and for Design Compiler
2023-10-24 14:01:43 -07:00
Rose Thompson
694ec18934
Added support for branch counters when there is no branch predictor.
2023-10-23 15:32:03 -05:00
Rose Thompson
1611d5ec3c
Fixed issue 250. instruction classification was not correct for jalr ra (non zero).
2023-10-23 15:30:43 -05:00
David Harris
6e7c0547a1
Modified log2 coding to avoid synthesis warning
2023-10-19 11:16:02 -07:00
David Harris
48d42c1e7c
Removed unnecessary RV64 PWDATA muxing from AHB peripherals because LSU already replicates
2023-10-18 05:50:41 -07:00
David Harris
1a6e57f8c0
Renamed wally-config to config in many comments
2023-10-16 13:49:09 -07:00
David Harris
434d6b2c5c
minfo test working again with mconfigptr for RV64
2023-10-15 06:41:52 -07:00
Ross Thompson
e02d3577ec
Fixed issue #412
...
The root cause was DTLB miss leads to page fault exception with concurrent I$ miss. The HPTW hits all entries in the D$ and quickly faults. However the I$ is still waiting on the main memory.
The trap then interrupts the atomimicity of the bus fetch and breaks the next several instructions.
The simplest solution is to use CommittedF to delay Exceptions like with Interrupts. Note this cannot happen with CommittedM. If the ITLB misses and the D$ also need to fetch a from the bus an ITLB page fault exception will not trigger the trap until a few stages later.
2023-10-09 16:03:37 -05:00
David Harris
28752303be
Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there
2023-10-04 12:28:12 -07:00
David Harris
19a6bbb01b
UpdateDA cleanup: don't assert UpdateDA when there is no SVADU
2023-10-04 09:57:13 -07:00
David Harris
d526d28804
Added MENVCFG.HADE bit and updated SVADU to depend on this bit
2023-10-04 09:34:28 -07:00
Ross Thompson
f863cbf366
Actually fixed non-power of 2 issue with RAS.
...
Added RAS swapping to branch predictor scripts and configurations.
2023-09-27 12:25:05 -05:00
Ross Thompson
aeacb481aa
Fixed sutble RAS bug when the stack size was not a power of 2.
2023-09-27 12:00:47 -05:00
Ross Thompson
26e4f6c6ba
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-09-14 10:16:54 -05:00
Ross Thompson
11a3fd9314
Slight modification to cachefsm.
2023-09-05 14:07:58 -05:00
Ross Thompson
22c519f2df
Merge pull request #407 from davidharrishmc/dev
...
initial spill logic improvement
2023-09-05 13:29:37 -05:00
Ross Thompson
85ba53eeaf
Merge pull request #406 from magpyed/cachesim_fix
...
Properly gate LRUWriteEn with ~FlushStage
2023-09-05 11:10:58 -05:00
David Harris
8f12c6f9a1
initial spill logic improvement
2023-09-03 04:21:13 -07:00
David Harris
9747d122d2
tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker
2023-09-02 12:56:36 -07:00
Limnanthes Serafini
6c78942685
Properly gate LRUWriteEn with ~FlushStage
2023-09-01 23:31:02 -07:00
David Harris
e75ceb044f
Improved tlb and controller coverage; fixed exclusions on broken lines
2023-08-31 00:27:47 -07:00
Kevin Kim
e4b0ab1472
Merge branch 'openhwgroup:main' into synth_wrapper_gen
2023-08-28 09:03:10 -07:00
Kevin Kim
ea46280146
make synth integerates wrapper generation and runs synth on wrapper
2023-08-28 09:02:56 -07:00
Ross Thompson
d892afc574
Merge pull request #398 from davidharrishmc/dev
...
Completed basic tests of svnapot and svpbmt
2023-08-28 09:10:20 -05:00
David Harris
8d3ff59673
Completed basic tests of svnapot and svpbmt
2023-08-28 06:57:35 -07:00
Kevin Kim
dabd15e029
synth works
2023-08-26 21:11:21 -07:00
David Harris
7a092a2275
Fixed merge conflict for ZICBOP
2023-08-25 18:41:57 -07:00
David Harris
f7b50f4721
Preparing to merge with CBO* changes
2023-08-25 18:41:03 -07:00
David Harris
bd6eef2a51
Initial implementation of SVNAPOT and SVPBMT does not break regression
2023-08-25 18:33:08 -07:00
David Harris
c6631ef808
Added N and PBMT bits to MMU PTE
2023-08-24 19:44:46 -07:00
David Harris
0e16203cd8
Merge pull request #393 from ross144/main
...
Implemented and tested CBOZ instruction
2023-08-24 19:17:38 -07:00
David Harris
c45fbe1ffe
Merge pull request #394 from harshinisrinath1001/main
...
Improved testing of csri with priv.S!
2023-08-24 19:16:50 -07:00
harshinisrinath
c9112ff18d
Improved testing of csri with priv.S
2023-08-24 18:39:15 -07:00
Ross Thompson
99455ad851
Fixed minor performance bug with CBOZ.
2023-08-24 17:08:20 -05:00
Ross Thompson
914b6f9734
Now have CBOZ instructions working!
2023-08-24 16:47:35 -05:00
David Harris
f5dab9f2fe
Check for legal SATP mode values
2023-08-24 05:18:04 -07:00
Ross Thompson
00e65c4ae7
Oups there was a bug in the SATP fix. RV32GC was broken by the changes.
2023-08-23 09:42:46 -05:00
Ross Thompson
45a7dfba28
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-08-23 09:15:13 -05:00
