Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-03 02:05:21 +00:00
Code Issues Packages Projects Releases Wiki Activity
3,297 Commits 4 Branches 2 Tags 53 MiB
a8c9f504fa
Commit Graph

60 Commits

Author SHA1 Message Date
David Harris
a8c9f504fa Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt 2022-05-11 15:08:33 +00:00
David Harris
91472eb948 Removed M suffix from interrupts because they are generated asynchronously to pipeline 2022-05-11 14:41:55 +00:00
David Harris
7268ff1fd4 Changed loop variable in CLINT because of error only seen on VLSI 2022-05-03 10:10:28 +00:00
bbracker
afc38abe08 change how tristate I/O is spoofed in GPIO loopback test 2022-04-21 10:31:16 -07:00
David Harris
5c607f2b6b Simplified profile for UART boot; added warnings on UART Rx errors 2022-04-21 04:54:45 +00:00
Kip Macsai-Goren
1ba328324b Added GPIO loopback to let outputs cause interrupts 2022-04-18 07:22:49 +00:00
David Harris
462158ea92 LSU name cleanup 2022-04-18 03:18:38 +00:00
Ross Thompson
c16dec88de Increased uart baud rate to 230400. 
Added uart signals to debugger.
 2022-04-17 15:23:39 -05:00
Ross Thompson
7d0462dc59 UART and clock speed changes to support 30Mhz. 2022-04-12 17:56:36 -05:00
Ross Thompson
7abde2b566 Increazed fpga clock speed to 35Mhz. 
linux boot is much faster.
 2022-04-05 15:09:49 -05:00
Ross Thompson
0ed34b8e63 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-04 10:56:10 -05:00
Ross Thompson
64846c800e Constraint changes for 40Mhz wally. 2022-04-04 10:50:48 -05:00
Ross Thompson
d83db2cde5 Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz. 2022-04-04 09:57:26 -05:00
Ross Thompson
fd9a33e453 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-03 17:56:55 -05:00
Ross Thompson
d135866098 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-02 16:39:54 -05:00
Ross Thompson
aaf6ea8d8d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-02 16:35:59 -05:00
Ross Thompson
f58a1eff9e Fixed linting issues. 2022-04-01 15:20:45 -05:00
Ross Thompson
178ecaa451 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-01 12:50:34 -05:00
Ross Thompson
0340c0fd44 Added wave config 
added new signals to ILA.
 2022-04-01 12:44:14 -05:00
bbracker
36c30b14c1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 17:54:43 -07:00
bbracker
e60139d3ee fix lingering overrun error bug 2022-03-31 17:54:32 -07:00
Ross Thompson
cb945a6a6a Added PLIC to ILA. 2022-03-31 16:44:49 -05:00
Ross Thompson
1586f893b1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 16:30:55 -05:00
Ross Thompson
e81f317764 Notes on what to change in ram.sv. 2022-03-31 15:48:15 -05:00
bbracker
d32e1147bf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 13:46:32 -07:00
bbracker
34c94f150e simplify plic logic 2022-03-31 13:46:24 -07:00
Ross Thompson
dc48d84dd6 Modified clint to support all byte write sizes. 2022-03-31 11:31:52 -05:00
bbracker
54b9745a75 big interrupts refactor 2022-03-30 13:22:41 -07:00
Ross Thompson
3ac736e2d5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-30 11:09:44 -05:00
Ross Thompson
370a075fa1 Partial cleanup of memories. 2022-03-30 11:09:21 -05:00
Ross Thompson
fc2b4453ec rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory. 2022-03-29 23:48:19 -05:00
Ross Thompson
de2672231d Partial fix to allow byte write enables with fpga and still get a preload to work. 2022-03-29 19:12:29 -05:00
bbracker
150a7b234b tabs vs spaces disagreement 2022-03-24 17:11:41 -07:00
bbracker
9f60256f22 1st attempt at multiple channel PLIC 2022-03-24 17:08:10 -07:00
Ross Thompson
d8947fa616 cleanup of ram.sv 2022-03-11 18:09:22 -06:00
Ross Thompson
bdfca503fa Name cleanup. 2022-03-10 18:44:50 -06:00
Ross Thompson
5c16b65a16 simplified uncore's name for HWDATA. 2022-03-10 18:17:44 -06:00
Ross Thompson
543e10ab32 Moved subwordwrite to lsu directory. 2022-03-10 18:15:25 -06:00
Ross Thompson
54abd944e2 Simplified byte write enable logic. 2022-03-10 18:13:35 -06:00
Ross Thompson
50789f9ddd Byte write enables are passing all configs now. 2022-03-10 17:26:32 -06:00
Ross Thompson
f7df3a0666 Progress on the path to getting all configs working with byte write enables. 2022-03-10 17:02:52 -06:00
Ross Thompson
83133f8c47 Partially working byte write enables. Works for cache, but not dtim or bus only. 2022-03-10 16:11:39 -06:00
Ross Thompson
d5f524a15e Added byte write enables to cache SRAMs. 2022-03-10 15:48:31 -06:00
bbracker
b8fd06576c fix lint bugs in PLIC and UART 2022-02-22 05:04:18 +00:00
bbracker
e7934c585a change RX side of UART to aslo be LSB-first 2022-02-22 03:34:08 +00:00
Ross Thompson
27042f028e Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path. 2022-02-16 15:22:19 -06:00
David Harris
15fb7fee60 Cleaned up synthesis warnings 2022-02-11 01:15:16 +00:00
Ross Thompson
99bb281944 Updated fpga's bootloader to reflect the changes to the gpio address change. 2022-02-01 10:43:24 -06:00
David Harris
62e5c7fd13 Comments in LSU code about restructuring 2022-01-27 15:53:59 +00:00
David Harris
ca1f7ce5d3 Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00