Rose Thompson
aa15a63d9c
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-01-31 13:12:32 -06:00
David Harris
f37c7bb1f6
Incorporated RAM_LATENCY and BURST_EN as parameters rather than define in code. Still need to update testbench to use this
2024-01-30 06:27:18 -08:00
David Harris
45e2317636
Added Wally github address to header comments
2024-01-29 05:38:11 -08:00
Rose Thompson
4c2ba2b0b4
Added StoreStall back to csrc.
2024-01-18 14:43:34 -06:00
Rose Thompson
edc56c669e
Fixed bug 546. non-leaf non-zero PBMT bit raise page fault.
2024-01-05 17:10:14 -06:00
David Harris
2c2f692f3a
Moved forwarding logic into controller
2023-12-26 21:17:01 -08:00
David Harris
8eace30f49
Moved UnalignedPCNextF mux into IFU
2023-12-20 16:18:31 -08:00
Rose Thompson
9f4c32d49c
Merge branch 'main' of github.com:ross144/cvw
2023-12-13 20:32:59 -06:00
David Harris
6c017141c5
Renamed HADE to ADUE for Svadu
2023-12-13 11:49:04 -08:00
Rose Thompson
13bb5d845b
On the way to solving the store delay hazard.
2023-12-13 10:39:01 -06:00
David Harris
d3ce683e06
Removed other unused signals from Verilog
2023-11-20 23:37:56 -08:00
David Harris
8ba0336c6f
Removed unused addins, cleaned up configuration to support half precision on RV64gc, gate unused hazard inputs to reduce critical path in rv32e
2023-11-14 11:01:58 -08:00
naichewa
e3d8162279
harris code review 3
2023-11-01 10:14:15 -07:00
naichewa
d5d4f9d044
transferred spi changes in ECA-authorized commit
2023-10-12 13:36:57 -07:00
David Harris
d526d28804
Added MENVCFG.HADE bit and updated SVADU to depend on this bit
2023-10-04 09:34:28 -07:00
David Harris
bd6eef2a51
Initial implementation of SVNAPOT and SVPBMT does not break regression
2023-08-25 18:33:08 -07:00
Ross Thompson
a89a1e675c
Merge branch 'boot' into mergeBoot
...
Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Jacob Pease
b3aaa87cba
Modified bootloader to access GUID partitions. SDC interrupt to PLIC.
...
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.
The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself was modified to accept the
SDC interrupt signal.
2023-07-14 13:36:44 -05:00
David Harris
afe66d0ee4
Added prefetch instructions; sent cbo instructions to LSU
2023-07-02 10:55:35 -07:00
David Harris
723b8266cb
Added prefetch signals
2023-07-02 10:06:58 -07:00
David Harris
482e4e6e92
Enhanced decoder to produce individual CMOpE output for the 4 CMO instructions
2023-07-02 09:35:05 -07:00
David Harris
b6ae5661b4
Added environment configuration control (menvcfg/senvcfg) of cbo instructions
2023-07-02 01:52:25 -07:00
David Harris
15314a9c9a
Gated floating-point load/stores with STATUS_FS and added initial decoding for Cache Management Operations
2023-07-02 00:34:30 -07:00
Ross Thompson
4428babda9
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-06-15 15:38:38 -05:00
Ross Thompson
85567841eb
Merge branch 'testbench-params2'
2023-06-15 15:31:13 -05:00
Ross Thompson
d2219023c3
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-06-15 14:57:23 -05:00
David Harris
9e839988dc
Gated MDU to save power; doesn't seem to have affected simulation time
2023-06-15 12:17:23 -07:00
David Harris
d3aebc00d4
Fixed UART merge conflict
2023-06-15 11:36:37 -07:00
Harshini Srinath
dd7c13cc2d
Update wallypipelinedsoc.sv
...
Program clean up
2023-06-15 10:39:37 -07:00
Harshini Srinath
b4469fd3bf
Update wallypipelinedcore.sv
...
Program clean up
2023-06-15 10:38:38 -07:00
Harshini Srinath
85a513e542
Update cvw.sv
...
Program clean up
2023-06-15 10:29:33 -07:00
David Harris
430537a052
Moved cvw.sv to src root directory to avoid double-compiling and producing a warning. Adjusted to files to reflect this.
2023-06-14 09:44:52 -07:00
Ross Thompson
ee4352975c
This parameterizes the testbench but does not use the verilator updates or the new testbench.
2023-06-12 11:00:30 -05:00
Ross Thompson
e27dfb8ce0
Merge branch 'verilator'
2023-06-11 15:28:04 -05:00
Ross Thompson
c7536663c0
Merge pull request #319 from davidharrishmc/dev
...
Renamed Performance Counter extension
2023-06-09 21:21:45 -04:00
David Harris
b70b0c7c5e
Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare
2023-06-09 14:40:01 -07:00
David Harris
df96900aa1
Added named support for Zicntr and Zihpm
2023-06-09 09:35:51 -07:00
Ross Thompson
a8a8422557
Updated parameterization types. Modelsim version 2022.1 did requires defaults to a 32 bit integer. The base and ranges for the address decoder need to be larger.
2023-06-09 09:28:24 -05:00
Ross Thompson
1ceea51d8b
Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet.
2023-05-31 16:51:00 -05:00
Ross Thompson
a963f0af3a
Updated source code to be compatible with verilator 5.011 for lint only.
2023-05-31 10:44:23 -05:00
Ross Thompson
1315a0bf4a
Got the branch predictor parameterized using Lim's method. Also had to add a global enum included in both cvw.sv and the configs which defines the branch predictor types. This should be synthesizable, but I'll need to double check.
2023-05-26 16:00:14 -05:00
Jacob Pease
40f81d5da6
The Vivado-RISC-V SDC works. Wally is now booting through it.
2023-05-26 15:42:33 -05:00
Ross Thompson
b517a96261
Update top level parameterized. Simulation slowed down to 4.5 minutes.
2023-05-26 12:13:11 -05:00
Ross Thompson
8cf38b28aa
The privileged unit is parameterized using Lim's method.
2023-05-26 12:03:46 -05:00
Ross Thompson
02a788a083
PMA checker's address decoder is now parameterized. I did not see bit slicing in Lim's code. I'm not sure how they got around this issue.
2023-05-26 11:06:48 -05:00
Ross Thompson
fcb1c63f5f
Partial parameterization into mmu.
2023-05-24 16:12:41 -05:00
Ross Thompson
5f5f33787d
MDU and hazard unit now also parameterized. Based on Lim's work. Again I want to clarify this their work. Not mine. I'm just doing this because the merge had an issue.
2023-05-24 15:01:35 -05:00
Ross Thompson
1299319d0b
More parameterization. Based on Lim's work. EBU, IFU (except bpred), and IEU done.
2023-05-24 14:56:02 -05:00
Ross Thompson
b91b54589e
Updated a large number of the source files to use parameters rather than `defines. Based on Lim's work. So far there is no simulation slow down.
2023-05-24 14:05:44 -05:00
Ross Thompson
930fb67308
Trying to figure out why the parameterization slowed down modelsim so much.
2023-05-24 12:44:42 -05:00
