David Harris
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8a910aabf4
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Documentation and comment fixes
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2024-11-27 05:42:39 -08:00 |
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David Harris
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028ffe9f4a
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Removing obsolete ***
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2024-11-20 07:23:51 -08:00 |
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David Harris
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147f62d9a5
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Fixed timer offset in RV32 WALLY-wfi; simplified in RV64 WALLY-wfi
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2024-11-17 06:43:13 -08:00 |
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David Harris
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205db4348c
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Fixed cause_m_time_interrupt most significant byte
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2024-11-16 18:31:02 -08:00 |
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naichewa
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73c2165756
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recommit sckmode 10 11 delay regression tests
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2024-11-05 11:30:13 -08:00 |
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naichewa
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9822902a4f
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Revert "Added SCKMODE 10 and 11 delay cases to regression tests"
unwanted submodule changes
This reverts commit 38a88862ac.
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2024-11-05 11:17:01 -08:00 |
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naichewa
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38a88862ac
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Added SCKMODE 10 and 11 delay cases to regression tests
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2024-11-04 16:22:42 -08:00 |
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naichewa
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3fda7ecb81
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Fix SPI regression tests
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2024-11-01 13:09:41 -07:00 |
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naichewa
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960d72295c
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Removed SPI hardware interlock test cases
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2024-11-01 11:27:41 -07:00 |
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David Harris
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1c1acc467e
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Tweaked SPI to avoid breaking VCS, but the SCLK divider still doesn't produce the right frequency and SCLKenableEarly looks like it wouldn't work for SckDiv = 0
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2024-10-26 02:01:09 -07:00 |
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Rose Thompson
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8fb1673ab3
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Updated email address authorship for my files.
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2024-10-15 10:27:53 -05:00 |
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naichewa
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3b7661dfd5
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SckDiv Zero bug fixes
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2024-09-03 14:58:46 -07:00 |
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Jacob Pease
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d8b75440b6
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With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests.
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2024-08-20 16:24:37 -05:00 |
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David Harris
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b3661a0af4
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Removed unused WALLY-lrsc reference outputs that were incorrect and are not used because Sail is the reference instead
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2024-03-24 12:31:49 -07:00 |
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David Harris
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824bc0dab7
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Fixed expected value on WALLY-satp-invalid
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2024-02-16 11:12:57 -08:00 |
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Rose Thompson
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6110799a1e
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Updated the wally rv32 priv tests to not use sail.
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2024-02-16 11:39:06 -06:00 |
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David Harris
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b362320dd9
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Removed unused Makefiles and Makefrags from wally-riscv-arch-test now that it is only used by riscof
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2024-02-16 06:46:49 -08:00 |
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David Harris
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d9003da8e0
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Moved some tests to wally-riscv-arch-test list that are simulated
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2024-01-30 10:28:51 -08:00 |
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naichewa
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8b60992e72
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fixed SPI tests failing when no icache
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2024-01-17 14:38:11 -08:00 |
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David Harris
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caedab679a
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Rewrote testbench to count signature entries rather than looking for x; this will facilitate Verilator which does not use x
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2024-01-07 07:14:12 -08:00 |
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Rose Thompson
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1b59182d59
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Updated tests with ending label.
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2023-12-20 14:55:37 -06:00 |
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Rose Thompson
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418ae0decc
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Fixed some regression tests with David's help.
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2023-12-19 14:18:21 -06:00 |
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David Harris
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6c017141c5
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Renamed HADE to ADUE for Svadu
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2023-12-13 11:49:04 -08:00 |
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naichewa
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d67badfc60
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fix hardware interlock, hold mode deassert
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2023-11-08 15:20:51 -08:00 |
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naichewa
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a5837eb62c
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fifo fixes and edge case testing
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2023-11-07 17:59:46 -08:00 |
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naichewa
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7dd3f24d6c
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Merge branch 'main' into spi
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2023-10-30 17:01:41 -07:00 |
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David Harris
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f6a7f707bd
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Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
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2023-10-30 09:56:17 -07:00 |
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Rose Thompson
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0fd5b3b2ce
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Updated comments in the cboz tests.
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2023-10-20 15:15:47 -05:00 |
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Rose Thompson
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5a4028064a
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Updated comments for the cbom tests.
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2023-10-20 15:13:52 -05:00 |
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naichewa
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0ff9ce527d
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Merge branch 'main' into spi
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2023-10-16 22:59:50 -07:00 |
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David Harris
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ac4216b43d
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Incorporated new AMO tests from riscv-arch-test
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2023-10-16 10:25:45 -07:00 |
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David Harris
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6245748ed7
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Added CSR permission tests for mconfigptr, menvcfg, mseccfg, etc.
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2023-10-15 15:31:03 -07:00 |
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David Harris
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b4891d88db
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Added WALLY minfo test for rv32
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2023-10-15 06:48:22 -07:00 |
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naichewa
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aa5abfc8e8
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always working after reg bit swizzle changes
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2023-10-13 14:22:32 -07:00 |
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naichewa
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f231c3d3a3
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correct delay0, fmt register test entries
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2023-10-12 15:13:23 -07:00 |
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naichewa
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d5d4f9d044
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transferred spi changes in ECA-authorized commit
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2023-10-12 13:36:57 -07:00 |
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David Harris
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d526d28804
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Added MENVCFG.HADE bit and updated SVADU to depend on this bit
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2023-10-04 09:34:28 -07:00 |
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David Harris
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8d3ff59673
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Completed basic tests of svnapot and svpbmt
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2023-08-28 06:57:35 -07:00 |
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Ross Thompson
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cd3349bd26
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Added rv32 cboz test.
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2023-08-24 17:02:53 -05:00 |
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Ross Thompson
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7d51690b7c
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Oups forgot to include the 32-bit cbom test in previous commit.
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2023-08-24 09:04:41 -05:00 |
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Ross Thompson
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310b700550
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Have a working 32 bit cbom test!
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2023-08-21 13:46:09 -05:00 |
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David Harris
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c137a1c8cf
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Fixed timer interrupt testing
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2023-06-09 17:20:41 -07:00 |
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David Harris
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f68b9c224a
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Fixed WALLY-trap test case to use menvcfg
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2023-06-09 15:24:26 -07:00 |
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David Harris
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b70b0c7c5e
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Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare
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2023-06-09 14:40:01 -07:00 |
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David Harris
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19096a812a
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Added Zifencei ISA to tests where necessary to support new compiler
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2023-05-16 11:18:27 -07:00 |
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David Harris
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0a7a159d69
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Added Zicsr and zifencei to RVTEST_ISA in custom tests where necessary to make them compile
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2023-05-14 06:58:29 -07:00 |
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Kip Macsai-Goren
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34200e8c76
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restored original virt mem tests when svadu is not supported
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2023-04-11 18:47:08 -07:00 |
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Kip Macsai-Goren
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c4766c8a02
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renamed virt mem tests to include svadu
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2023-04-11 18:46:37 -07:00 |
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Kip Macsai-Goren
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b2d6084eea
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removed unnecessary 'deadbeef's at the end of reference outputs
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2023-04-11 18:32:04 -07:00 |
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Kip Macsai-Goren
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a82c0a7780
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Modified virt mem tests to do correct r/w when svadu is enabled
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2023-04-11 18:08:30 -07:00 |
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